DCT
1:22-cv-01411
Cedar Lane Tech Inc v. Autel Robotics USA LLC
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Cedar Lane Technologies Inc. (Canada)
- Defendant: Autel Robotics USA LLC (Delaware)
- Plaintiff’s Counsel: Napoli Shkolnik LLC; Rabicoff Law LLC
- Case Identification: 1:22-cv-01411, D. Del., 10/26/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Delaware because Defendant is incorporated there, maintains an established place of business in the District, and has committed acts of patent infringement in the District.
- Core Dispute: Plaintiff alleges that Defendant’s drone products infringe three patents related to methods and systems for interfacing image sensors with data compression and processing hardware.
- Technical Context: The patents address the efficient transfer of digital image data from a sensor to memory and processing circuits, a foundational technology for digital cameras, scanners, and unmanned aerial vehicles (drones).
- Key Procedural History: U.S. Patent No. 8,537,242, a divisional of the application that led to U.S. Patent No. 6,972,790, was issued subject to a terminal disclaimer over the ’790 Patent, which may link their expiration dates. The complaint does not allege any pre-suit knowledge or mention other prior litigation.
Case Timeline
| Date | Event |
|---|---|
| 1999-06-01 | ’527 Patent Priority Date (Filing Date) |
| 2000-01-21 | ’790 and ’242 Patents Priority Date (Provisional) |
| 2002-10-29 | ’527 Patent Issued |
| 2005-12-06 | ’790 Patent Issued |
| 2013-09-17 | ’242 Patent Issued |
| 2022-10-26 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,473,527 - “Module and method for interfacing analog/digital converting means and JPEG compression means,” Issued October 29, 2002
The Invention Explained
- Problem Addressed: The patent’s background section describes that conventional systems for JPEG image compression required a costly external memory buffer (RAM) to sit between the analog-to-digital (A/D) converter and the JPEG compression chip. This was necessary to manage different data rates and to assemble image data into the specific block format (e.g., 8x8 pixels) that the JPEG algorithm requires (’527 Patent, col. 1:35-49).
- The Patented Solution: The invention proposes an interface module that eliminates the need for this separate, external RAM. The module uses a smaller, internal memory device sized to hold a specific number of image lines (e.g., eight lines). It reads these lines from the A/D converter, stores them, and then feeds formatted image blocks (e.g., 8x8 pixels) directly to the JPEG compression device, which has its own compatible internal memory. This memory management approach streamlines the hardware architecture (’527 Patent, col. 2:1-24; Fig. 2).
- Technical Importance: The described solution aimed to reduce the component count, cost, and complexity of digital imaging devices like scanners and early digital cameras by removing a discrete memory chip from the design (’527 Patent, col. 1:47-49).
Key Claims at a Glance
- The complaint does not specify which claims are asserted, instead incorporating by reference charts from an unattached exhibit (Compl. ¶15). The analysis here focuses on representative independent claims 1 (a module) and 8 (a method).
- Independent Claim 1 requires, in part:
- A "read control means" for reading a "predetermined number of image lines" from an A/D converter.
- A "memory means" for storing those image lines, with a capacity matching the "built-in memory device" of a JPEG compression means.
- An "output control means" for reading an "image block" from the memory means and forwarding it to the JPEG compression means.
- The complaint reserves the right to assert additional claims (Compl. ¶13).
U.S. Patent No. 6,972,790 - “Host interface for imaging arrays,” Issued December 6, 2005
The Invention Explained
- Problem Addressed: The patent identifies a fundamental incompatibility between the continuous, synchronized "video style" data stream produced by CMOS image sensors and the asynchronous, random-access interface of commercial microprocessors. Bridging this gap conventionally required "additional glue logic," which increased cost and complexity, diminishing the benefits of using integrated CMOS sensors (’790 Patent, col. 1:12-46, 1:60-63).
- The Patented Solution: The patent describes an interface, preferably integrated on the same silicon die as the image sensor, that acts as a smart buffer. It uses a memory (such as a First-In-First-Out or FIFO buffer) to receive data at the sensor's clock rate. When the amount of data in the memory reaches a certain level, a signal generator alerts the main processor (e.g., via an interrupt), which then reads the data from the buffer at its own pace. This decouples the timing of the sensor and the processor (’790 Patent, Abstract; col. 3:11-20).
- Technical Importance: This on-chip interface approach enables the seamless and low-cost integration of CMOS image sensors with standard microprocessors, a key step in the development of compact and affordable digital imaging systems (’790 Patent, col. 1:60-66).
Key Claims at a Glance
- The complaint incorporates by reference charts from an unattached exhibit to identify asserted claims (Compl. ¶24). The analysis here focuses on representative independent claims 1 (an interface) and 15 (an integrated circuit).
- Independent Claim 1 requires, in part:
- A "memory" for storing imaging array data.
- A "signal generator" for generating a signal for the processor "in response to the quantity of data in the memory".
- A "circuit for controlling the transfer" of data from the memory at a rate determined by the processor.
- The complaint reserves the right to assert additional claims (Compl. ¶19).
Multi-Patent Capsule: U.S. Patent No. 8,537,242 - “Host interface for imaging arrays,” Issued September 17, 2013
- Technology Synopsis: As a divisional of the '790 Patent, the '242 Patent shares the same specification and addresses the same problem of efficiently interfacing a CMOS image sensor with a processor system. The solution described involves an on-chip interface with a memory buffer and control logic that manages the asynchronous data transfer by generating a signal (e.g., an interrupt or bus request) to the processor when the buffer’s data content reaches a predetermined level (’242 Patent, Abstract; col. 1:10-20).
- Asserted Claims: The complaint does not specify claims, incorporating them by reference to an unattached exhibit (Compl. ¶33). Representative independent claims include 1 and 8.
- Accused Features: The complaint alleges infringement by "Exemplary Defendant Products" but does not specify which features are accused of infringing this particular patent, instead referring to the unattached exhibit (Compl. ¶¶ 28, 33).
III. The Accused Instrumentality
Product Identification
The complaint does not name specific accused products. It refers generally to "Exemplary Defendant Products" that are identified in charts within Exhibits 4, 5, and 6, which were not filed with the complaint (Compl. ¶¶ 13, 19, 28).
Functionality and Market Context
The complaint provides no technical description of the accused products' functionality. It makes only the conclusory allegation that the products "practice the technology claimed" by the patents-in-suit (Compl. ¶¶ 15, 24, 33). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint does not provide claim charts, instead incorporating them by reference (Compl. ¶¶ 16, 25, 34). The following tables summarize the infringement theories for representative claims based on the patents’ disclosures, as the complaint itself lacks specific factual allegations mapping product features to claim elements.
’527 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a module for interfacing... said JPEG compression means having a built-in memory device | The complaint alleges Defendant's products contain an interface module between an image sensor and a compression engine. | ¶15 | col. 4:55-58 |
| read control means... for sequentially reading a predetermined number of image lines from a data output of said analog/digital converting means | The complaint’s theory suggests the products contain a component that reads a set number of image lines into a buffer. | ¶15 | col. 4:58-62 |
| memory means... for storing said predetermined number of image lines, said memory means capable of storing the same number of image lines as said built-in memory device | The complaint’s theory suggests the products use a memory buffer whose size is coordinated with the compression hardware. | ¶15 | col.4:3-8 |
| output control means... for sequentially reading an image block from said memory means and forwarding said image block to said built-in memory device | The complaint’s theory suggests a component reads formatted blocks of data from the buffer and sends them for compression. | ¶15 | col. 4:8-11 |
’790 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| An interface for receiving data from an image sensor... for transfer to a processor system | The complaint alleges Defendant's products contain an interface for transferring data from an image sensor to a processor. | ¶24 | col. 2:3-6 |
| a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals | The complaint’s theory suggests the products use a memory (e.g., a FIFO buffer) to store image data at the sensor's native speed. | ¶24 | col. 8:8-10 |
| a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory | The complaint’s theory suggests a component generates an interrupt or other system request when the data buffer reaches a certain fill level. | ¶24 | col. 8:11-14 |
| a circuit for controlling the transfer of the data from the memory at a rate determined by the processor system | The complaint’s theory suggests a control circuit manages the offloading of data from the buffer at the processor's speed, not the sensor's. | ¶24 | col. 8:15-18 |
Identified Points of Contention
- Scope Questions: A primary question for the ’527 Patent will be whether the terms "read control means" and "output control means", described in the patent as distinct logical blocks, can be read onto the highly integrated System-on-a-Chip (SoC) architecture of a modern drone, where such functions may be handled by a single processor running software.
- Technical Questions: A key evidentiary question for the ’790 and ’242 Patents will be whether the accused products generate a control signal specifically "in response to the quantity of data in the memory." The infringement case may depend on discovering evidence that the data transfer is triggered by the buffer's fill-level, rather than by a fixed schedule or other external timing signal.
V. Key Claim Terms for Construction
Term: "read control means" / "output control means" (’527 Patent)
Context and Importance
Practitioners may focus on these terms because the patent depicts them as distinct hardware blocks (Fig. 2, items 22 & 23). The defense may argue that the accused products, likely using a modern SoC, do not have these separate structures. The dispute will center on whether these terms require a specific hardware structure or can cover functions performed by a general-purpose processor.
Intrinsic Evidence for Interpretation
- Evidence for a Broader (Functional) Interpretation: The use of "means-plus-function" language in the claims suggests a focus on the recited function (e.g., "sequentially reading"), not a specific structure.
- Evidence for a Narrower (Structural) Interpretation: The specification consistently describes these as separate devices in the preferred embodiment (e.g., "It comprises a read control device 22, an output control device 23, and a memory device 24") which could be used to argue for a more limited, structural interpretation (’527 Patent, col. 2:49-51).
Term: "in response to the quantity of data in the memory" (’790 and ’242 Patents)
Context and Importance
Practitioners may focus on this term because it requires a specific causal link: the data level in the buffer must trigger the signal to the processor. This distinguishes the invention from systems that transfer data based on other triggers, such as a simple timer. Proving this causal relationship in the accused products will be critical for the Plaintiff.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The claim language is general and does not specify how the quantity is measured or what the threshold is, potentially covering any mechanism where buffer fullness is a trigger.
- Evidence for a Narrower Interpretation: The detailed description discloses a specific embodiment where an "increment/decrement counter" (54) tracks the data, and its output (Sc) is compared to a "FIFO limit" (Sl) to generate an interrupt signal. A defendant could argue this specific implementation limits the scope of the claim term (’790 Patent, col. 6:11-15; Fig. 2).
VI. Other Allegations
Indirect Infringement
The complaint alleges induced infringement for the ’790 and ’242 Patents. The factual basis alleged is that Defendant distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" the patents (Compl. ¶¶ 22, 31).
Willful Infringement
The complaint does not use the word "willful" but lays the groundwork for a claim of post-suit willfulness for the ’790 and ’242 Patents. It alleges that the filing of the complaint provides "Actual Knowledge of Infringement" and that Defendant continues to infringe "Despite such actual knowledge" (Compl. ¶¶ 21-22, 30-31). No allegations of pre-suit knowledge are made.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of architectural mapping: can the functional elements described in the patents, particularly the discrete "read control means" and "output control means" of the ’527 Patent, be mapped onto the highly integrated, software-driven System-on-a-Chip (SoC) architectures found in modern drone technology? This raises a fundamental question of whether a functional description in a patent claim can read on a system where those functions are consolidated into a single, programmable processor.
- A second central issue will be one of evidentiary proof: given the complaint’s reliance on non-public exhibits and its lack of specific technical allegations, the case will likely turn on what is revealed in discovery. Can the Plaintiff find concrete evidence within the accused products' hardware or source code of the specific triggering mechanism required by the '790 and '242 Patents—namely, a signal generated "in response to the quantity of data in the memory"—or will discovery show a different, non-infringing method of data-transfer control?