DCT

1:22-cv-01512

Synopsys Inc v. Bell Semiconductor LLC

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:22-cv-01512, D. Del., 11/18/2022
  • Venue Allegations: Venue is alleged to be proper in the District of Delaware based on Defendant’s incorporation in the state and its purposeful availment of the court system by filing other patent infringement lawsuits in the district.
  • Core Dispute: Plaintiffs, major electronic design automation (EDA) software providers, seek a declaratory judgment of non-infringement and invalidity of six patents owned by Defendant, arguing their EDA tools do not perform the patented methods related to semiconductor design.
  • Technical Context: The lawsuit concerns Electronic Design Automation (EDA) software, which provides the fundamental tools used by engineers to design, verify, and test complex semiconductor chips.
  • Key Procedural History: This action arises from a large-scale litigation campaign initiated by Defendant Bell Semiconductor (BSLLC) against at least twenty-five customers of Plaintiffs Synopsys and Cadence, involving over eighty-seven district court lawsuits and three ITC investigations. The complaint notes that a prior ITC investigation involving one of the asserted patents was terminated after BSLLC withdrew its complaint, allegedly due to a procedural schedule that would conclude after the patent's expiration.

Case Timeline

Date Event
2000-01-18 U.S. Patent No. 6,436,807 Priority Date
2002-08-20 U.S. Patent No. 6,436,807 Issue Date
2003-07-31 U.S. Patent No. 7,007,259 Priority Date
2004-09-22 U.S. Patent No. 7,149,989 Priority Date
2004-10-10 U.S. Patent No. 7,260,803 Priority Date
2004-11-17 U.S. Patent No. 7,396,760 Priority Date
2004-12-17 U.S. Patent No. 7,231,626 Priority Date
2006-02-28 U.S. Patent No. 7,007,259 Issue Date
2006-12-12 U.S. Patent No. 7,149,989 Issue Date
2007-06-12 U.S. Patent No. 7,231,626 Issue Date
2007-08-21 U.S. Patent No. 7,260,803 Issue Date
2008-07-08 U.S. Patent No. 7,396,760 Issue Date
2022-04-27 BSLLC begins litigation campaign against Plaintiffs' customers
2022-11-18 Complaint for Declaratory Judgment Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,007,259 - Method for Providing Clock-Net Aware Dummy Metal Using Dummy Regions

The Invention Explained

  • Problem Addressed: The patent addresses a problem in semiconductor manufacturing where Chemical Mechanical Polishing (CMP), a process used to flatten chip layers, can cause uneven polishing known as "dishing" in areas with low metal density (Compl. ¶26). To prevent this, non-functional "dummy metal" is added. However, placing this dummy metal near timing-sensitive "clock nets" can introduce parasitic capacitance, degrading chip performance, while prior methods to avoid this were allegedly inefficient and required multiple, iterative runs of the fill tool (’259 Patent, col. 1:51-67; Compl. ¶28). The complaint provides a diagram illustrating the post-CMP "dishing" phenomenon, where sparse areas of a semiconductor design are over-polished compared to dense areas (Compl. p. 17).
  • The Patented Solution: The invention describes a software-based method that intelligently places dummy metal to meet density requirements while protecting clock net timing ('259 Patent, Abstract). The algorithm identifies empty spaces ("dummy regions") and prioritizes them so that regions located adjacent to critical clock nets are filled with dummy metal last, after other regions have already been filled ('259 Patent, col. 2:32-36).
  • Technical Importance: This approach aimed to achieve the required metal density for successful CMP in a single, non-iterative software run, while minimizing the negative timing impact on the most critical signal paths in the design ('259 Patent, col. 2:15-21).

Key Claims at a Glance

  • The complaint seeks a declaratory judgment of non-infringement for all claims, referencing BSLLC's allegations against claims 1-17 and 35-37 (Compl. ¶¶51, 93). Independent claim 1 is representative.
  • Essential elements of independent claim 1 include:
    • Identifying free spaces on a layer of a circuit design suitable for dummy metal insertion as dummy regions.
    • Prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.
  • The complaint reserves the right to address all claims of the patent (Compl. ¶92).

U.S. Patent No. 6,436,807 - Method for Making an Interconnect Layer and a Semiconductor Device Including the Same

The Invention Explained

  • Problem Addressed: This patent also addresses the need for uniform layer density to facilitate CMP. It notes that the process of depositing dielectric material can create "protrusions" over the underlying metal features. The size of these protrusions can vary depending on the deposition process, leading to a non-planar surface that is difficult to polish uniformly (’807 Patent, col. 1:36-49).
  • The Patented Solution: The patent describes a method for creating an interconnect layer layout by first determining the density of existing "active interconnect features" in different regions ('807 Patent, Abstract). It then adds "dummy fill features" to achieve a desired overall density. Critically, the method includes the step of "defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias," meaning the size of the added dummy features is calculated based on the physical characteristics of the manufacturing process to ensure proper planarization ('807 Patent, col. 7:1-5).
  • Technical Importance: The invention provides a method for calculating dummy fill that accounts not only for the open space available but also for the physical, process-dependent artifacts ("deposition bias") that affect planarity, suggesting a more precise approach to achieving uniformity ('807 Patent, col. 2:27-35).

Key Claims at a Glance

  • The complaint seeks a declaratory judgment of non-infringement for all claims, referencing BSLLC's allegations against claims 1-18 (Compl. ¶¶59, 109). Independent claim 1 is representative.
  • Essential elements of independent claim 1 include:
    • Determining an active interconnect feature density for each of a plurality of layout regions.
    • Adding dummy fill features to each layout region to obtain a desired density.
    • The adding step comprises defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias.
  • The complaint reserves the right to address all claims of the patent (Compl. ¶108).

Multi-Patent Capsules

  • *U.S. Patent No. 7,396,760, "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits", issued July 8, 2008*

    • Technology Synopsis: The patent describes a method for reducing electrical capacitance between different layers of a semiconductor chip. It achieves this by inserting dummy metal fill objects in a manner that minimizes the physical overlap of those objects when viewed across adjacent layers, for instance by arranging them in a checkerboard pattern (Compl. ¶¶33-34; ’760 Patent, Abstract).
    • Asserted Claims: BSLLC has asserted claims 1-19 (Compl. ¶101).
    • Accused Features: Plaintiffs' EDA tools are accused of infringing by allegedly performing methods to "determine... an overlap" and "minimize... the overlap by re-arranging" dummy fill features on adjacent layers (Compl. ¶101).

  • *U.S. Patent No. 7,260,803, "Incremental Dummy Metal Insertions", issued August 21, 2007*

    • Technology Synopsis: This patent relates to a method for efficiently updating dummy metal fill after a design has been changed. Instead of re-running the entire fill process, the invention proposes a method to simply check whether any previously inserted dummy metal objects now intersect with new or moved objects in the design data, and then deleting only those that intersect (Compl. ¶¶29-30; ’803 Patent, Abstract).
    • Asserted Claims: BSLLC has asserted claims 1-11 (Compl. ¶105).
    • Accused Features: Plaintiffs' EDA tools are accused of infringing by allegedly performing a check for intersecting dummy metal objects after a design change to avoid having to rerun the entire dummy fill tool (Compl. ¶105).

  • *U.S. Patent No. 7,231,626, "Method of Implementing an Engineering Change Order in an Integrated Circuit Design by Windows", issued June 12, 2007*

    • Technology Synopsis: The patent describes a method for implementing an Engineering Change Order (ECO) in a chip design more efficiently. It does so by creating a "window" that encloses only the portion of the design affected by the change and then performing the necessary re-routing of electrical connections exclusively within that window, rather than re-routing the entire design (Compl. ¶¶35-36; ’626 Patent, Abstract).
    • Asserted Claims: BSLLC has asserted claims 1-4 (Compl. ¶97).
    • Accused Features: Plaintiffs' EDA tools are accused of infringing by allegedly performing "an incremental routing of the integrated circuit design only for each net... that is enclosed by the window" (Compl. ¶97).

  • *U.S. Patent No. 7,149,989, "Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design", issued December 12, 2006*

    • Technology Synopsis: This patent discloses a method for performing early-stage design validation to find "texted metal short circuits" (short circuits identified by conflicting text labels on the same electrical net). The method's key feature is generating and using a "specific rule deck" that is a smaller subset of the full design rule deck, allowing for a faster, targeted check early in the design process (Compl. ¶¶37-38; ’989 Patent, Abstract).
    • Asserted Claims: BSLLC has asserted claims 1-6 (Compl. ¶113).
    • Accused Features: Plaintiffs' EDA tools are accused of infringing by allegedly generating "a specific rule deck from the physical design rule deck" to perform targeted checks for texted metal short circuits (Compl. ¶113).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Plaintiffs' Electronic Design Automation (EDA) software products, which BSLLC has allegedly identified as the basis for infringement in its lawsuits against Plaintiffs' customers (Compl. ¶¶13, 17). Specific products named include Synopsys' IC Compiler, IC Compiler II, and IC Validator, as well as Cadence's Innovus, Virtuoso, Pegasus, and PVS products (Compl. ¶¶3-6, 93).

Functionality and Market Context

The accused products are described as comprehensive software tools that engineers use to design, develop, and test semiconductor chips (Compl. ¶2). The relevant functionalities alleged in the various infringement theories include place-and-route (placing gates and routing wires), physical verification (including Design Rule Checking and metal fill generation), and implementing design changes (Compl. ¶¶3-6). The complaint asserts that Plaintiffs Synopsys and Cadence are the "two largest suppliers" of these tools in the world, and that BSLLC's litigation campaign is targeted at customers for their use of these specific tools (Compl. ¶¶2, 13).

IV. Analysis of Infringement Allegations

Because this is a declaratory judgment action, the infringement analysis is based on Plaintiffs' denials that their products perform the claimed steps.

U.S. Patent No. 7,007,259 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality (as denied by Plaintiffs) Complaint Citation Patent Citation
identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; and The complaint does not contest that the tools identify free spaces for dummy fill. N/A col. 5:28-31
prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets. Plaintiffs' EDA tools, when used by customers, do not "prioritiz[e] the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last" to minimize timing impact. ¶93 col. 5:32-36

U.S. Patent No. 6,436,807 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality (as denied by Plaintiffs) Complaint Citation Patent Citation
determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout; and The complaint does not contest that the tools may determine feature density. N/A col. 7:62-63
adding dummy fill features to each layout region to obtain a desired density of active interconnect features and dummy fill features... The complaint does not contest that the tools add dummy fill to achieve a desired density. N/A col. 7:64-65
the adding comprising defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias... Plaintiffs' EDA design tools, when used by customers, do not "add[] dummy fill features ... [where] the adding compris[es] defining a minimum dummy fill lateral dimension based upon a dielectric layer deposition bias." ¶109 col. 7:1-5
  • Identified Points of Contention:
    • Technical Questions: A primary point of contention for the ’259 patent will be a factual and technical one: what is the actual algorithm used by Plaintiffs' EDA tools for prioritizing dummy fill placement? The dispute will center on whether the accused tools' complex optimization routines perform the specific function of filling regions adjacent to clock nets "last," as required by the claim language (Compl. ¶93).
    • Scope Questions: For the ’807 patent, a key dispute will concern claim scope. The infringement question raises the issue of whether the claim term "dielectric layer deposition bias"—a term rooted in a physical manufacturing artifact—can be construed to cover the potentially more abstract, design-stage parameters that Plaintiffs' software tools may use to determine dummy fill dimensions (Compl. ¶109).

V. Key Claim Terms for Construction

  • Term from the ’259 Patent: "prioritizing ... such that the dummy regions located adjacent to clock nets are filled with dummy metal last"

    • Context and Importance: This functional phrase is the core of the asserted independent claim. The infringement determination will likely depend entirely on whether the accused tools' operation meets this specific, ordered sequence. Practitioners may focus on this term because the word "last" implies a strict, final step in a sequence, which may or may not align with the complex, multi-variable heuristic algorithms used in modern EDA tools.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification discusses the general goal of minimizing timing impact, which a party could argue is achieved by any method that de-prioritizes clock net regions, not necessarily one that fills them absolutely last ('259 Patent, col. 2:19-21).
      • Evidence for a Narrower Interpretation: The claim language itself is explicit ("last"). The abstract states, "the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last," reinforcing this specific order as central to the invention ('259 Patent, Abstract). The detailed description of the preferred embodiment also describes sorting regions so that clock-net adjacent regions are placed later in the list for filling ('259 Patent, col. 6:35-48).

  • Term from the ’807 Patent: "dielectric layer deposition bias"

    • Context and Importance: The infringement analysis for the ’807 patent hinges on this term, as it defines the specific input allegedly used to calculate the size of dummy features. Its construction will determine whether the parameters used by the accused tools fall within the claim's scope.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The term "bias" could be argued to encompass any systematic deviation or factor accounted for in the deposition process, potentially broadening its meaning beyond a single, specific measurement.
      • Evidence for a Narrower Interpretation: The specification provides concrete examples of this "bias," describing it as physical "protrusions" over interconnect features that result from specific deposition processes like HDP-CVD ('807 Patent, col. 1:36-49). The patent distinguishes between "negative bias" (protrusion is narrower than the feature) and "positive bias" (protrusion is wider), tying the term directly to measurable, physical manufacturing effects ('807 Patent, col. 1:45-49, col. 2:41-48).

VI. Other Allegations

  • Indirect Infringement: The complaint seeks a declaratory judgment that Plaintiffs do not directly or indirectly infringe (Compl. ¶¶92, 96). BSLLC's underlying suits against Plaintiffs' customers allege direct infringement by the customers and, implicitly, indirect infringement (inducement or contribution) by Plaintiffs as the suppliers of the accused EDA tools (Compl. ¶¶13, 47). Plaintiffs' core defense is that because their tools do not perform the claimed methods, there can be no direct infringement by their customers to induce or contribute to (Compl. ¶¶93, 109).
  • Willful Infringement: While this is a DJ action and Plaintiffs are not accused of willfulness, the complaint notes that BSLLC seeks enhanced damages from the customers in the underlying suits, which requires a finding of willful infringement (Compl. ¶¶48, 61). The complaint establishes a timeline of BSLLC's litigation campaign, which would serve as evidence of pre-suit knowledge for any customer sued after the initial wave of suits began on April 27, 2022 (Compl. ¶45).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of algorithmic functionality: Do the accused EDA tools' sophisticated routines for placing dummy metal perform the specific, ordered prioritization ("fill adjacent to clock nets last") required by the ’259 patent, or is there a fundamental mismatch in technical operation between the patent's prescribed method and the accused software's real-world function?
  • A key evidentiary question will be one of definitional scope: Can the term "dielectric layer deposition bias," which the ’807 patent ties to specific physical artifacts of the manufacturing process, be construed broadly enough to read on the design-stage parameters and algorithms that the accused EDA software actually uses to determine dummy fill characteristics?
  • A significant threshold question for the court will be procedural and jurisdictional: Given the sprawling, multi-jurisdictional litigation campaign detailed in the complaint, does this declaratory judgment action present a proper and more efficient vehicle for resolving the central technology disputes for all parties under the customer-suit exception, or should the issues be adjudicated in the dozens of separate, later-filed customer lawsuits?