DCT

1:22-cv-01569

Siemens Industry Software Inc v. Bell Semiconductor LLC

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: Siemens Industry Software Inc v. Bell Semiconductor LLC, 1:22-cv-01569, D. Del., 12/02/2022
  • Venue Allegations: Plaintiff alleges venue is proper in Delaware as it is Defendant’s state of incorporation and a district where Defendant has filed numerous patent lawsuits, thereby purposefully availing itself of the jurisdiction.
  • Core Dispute: Plaintiff, a supplier of Electronic Design Automation (EDA) software, seeks a declaratory judgment that its products do not infringe Defendant's patents, following a widespread litigation campaign where Defendant sued Plaintiff's customers for infringement based on their use of Plaintiff's tools.
  • Technical Context: The technology involves EDA software used to design and verify complex semiconductor chips, with the patents-in-suit directed to specific processes like managing "dummy metal fill" for manufacturability, implementing engineering changes, and validating designs.
  • Key Procedural History: The complaint follows Defendant's litigation campaign against at least 18 of Plaintiff's customers in over 66 district court cases and multiple International Trade Commission (ITC) investigations. One ITC investigation concerning the ’259 patent was voluntarily terminated by Defendant after the ITC set a schedule that would conclude after the patent's expiration date. The complaint also asserts that Plaintiff holds a license to the ’807 patent through a 2001 agreement with Defendant's predecessor-in-interest.

Case Timeline

Date Event
2000-01-18 ’807 Patent Priority Date
2002-08-20 ’807 Patent Issue Date
2003-07-31 ’259 Patent Priority Date
2003-10-10 ’803 Patent Priority Date
2004-09-22 ’989 Patent Priority Date
2004-11-17 ’760 Patent Priority Date
2004-12-17 ’626 Patent Priority Date
2006-02-28 ’259 Patent Issue Date
2006-12-12 ’989 Patent Issue Date
2007-06-12 ’626 Patent Issue Date
2007-08-21 ’803 Patent Issue Date
2008-07-08 ’760 Patent Issue Date
2022-04-28 ITC Investigation on ’259 Patent initiated by Defendant
2022-08-29 ITC Investigation on ’259 Patent terminated at Defendant’s request
2022-12-02 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,007,259 - "Method for Providing Clock-Net Aware Dummy Metal Using Dummy Regions"

Issued February 28, 2006

The Invention Explained

  • Problem Addressed: In semiconductor manufacturing, inserting "dummy metal" into empty spaces on a chip layer is necessary to ensure uniform planarity during polishing. However, this added metal increases parasitic capacitance, which can slow down critical timing circuits, particularly the "clock nets" that synchronize the chip's operations (’259 Patent, col. 1:40-57). Simply programming a tool to maintain a large "stay-away" distance from clock nets is inefficient and may prevent the design from meeting required metal density levels (’259 Patent, col. 2:1-14).
  • The Patented Solution: The invention describes a software method that intelligently prioritizes the order of filling empty spaces, or "dummy regions." It specifically teaches filling the dummy regions located adjacent to clock nets last. This ensures that if the minimum metal density is met before all empty space is filled, the areas most critical to timing are the ones left empty, thereby minimizing negative timing impacts (’259 Patent, Abstract; col. 2:32-47). The method can be further refined to fill regions adjacent to wider, more critical clock nets later than those adjacent to narrower, less critical ones (’259 Patent, col. 2:35-39).
  • Technical Importance: This approach provided a more nuanced way to meet manufacturing density rules while protecting the performance of high-speed, timing-sensitive integrated circuits (’259 Patent, col. 2:19-23).

Key Claims at a Glance

  • The complaint asserts non-infringement of claims 1-17 and 35-37 (Compl. ¶91). Independent claims 1, 18, and 35 are representative.
  • Independent Claim 1 (Method):
    • Identifying free spaces on a layer of a circuit design as "dummy regions"
    • Prioritizing the dummy regions such that those located adjacent to clock nets are filled with dummy metal last
  • Independent Claim 18 (Computer-Readable Medium): Embodies the instructions for performing the method of Claim 1.
  • Independent Claim 35 (Method):
    • Identifying free spaces, determining which are adjacent to clock nets, assigning a timing factor, sorting, and
    • Inserting dummy metal into the sorted regions such that regions adjacent to "increasingly wider clock nets are filled last"

U.S. Patent No. 7,231,626 - "Method of Implementing an Engineering Change Order in an Integrated Circuit Design by Windows"

Issued June 12, 2007

The Invention Explained

  • Problem Addressed: When a late-stage change—an Engineering Change Order (ECO)—is required for a complex chip design, conventional methods require re-running time-consuming design, routing, and verification tools on the entire integrated circuit, even if the change is very small. This is highly inefficient (’626 Patent, col. 1:15-24).
  • The Patented Solution: The patent describes a method to isolate the ECO's impact. It involves creating a "window," or a bounded sub-area of the design, that encloses the change. Subsequent processing steps, such as routing the affected electrical nets, are then performed only within this window, rather than across the entire design (’626 Patent, Abstract; col. 3:26-40). This dramatically reduces the computation time needed to implement and verify the change.
  • Technical Importance: This "windowing" approach enabled designers to make targeted, late-stage fixes to complex chips far more quickly, saving significant time and computational resources in the design cycle (’626 Patent, col. 3:15-20).

Key Claims at a Glance

  • The complaint asserts non-infringement of claims 1-8 (Compl. ¶95). Independent claims 1 and 5 are representative.
  • Independent Claim 1 (Method):
    • Receiving an integrated circuit design and an ECO
    • Creating at least one "window" that encloses a change from the ECO, where the window is smaller than the entire design area
    • Performing an "incremental routing" of the design "only for each net... that is enclosed by the window"
    • Replacing the area in a copy of the design with the results of the incremental routing
  • Independent Claim 5 (Computer Readable Storage Medium): Embodies the instructions for performing the method of Claim 1.

U.S. Patent No. 7,396,760 - "Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits"

Issued July 8, 2008

  • Technology Synopsis: The patent addresses unwanted capacitance created by overlapping dummy fill features on successive metal layers. The solution involves analyzing pairs of layers and re-arranging the dummy fill patterns, for instance into a checkerboard, to minimize this overlap and its associated capacitance (Compl. ¶27; ’760 Patent, Abstract).
  • Asserted Claims: Claims 1-19 are implicated (Compl. ¶99).
  • Accused Features: The accused processes involve using Siemens' EDA tools to "rearrange dummy fill to minimize its overlap in successive layers" (Compl. ¶75).

U.S. Patent No. 7,260,803 - "Incremental Dummy Metal Insertions"

Issued August 21, 2007

  • Technology Synopsis: The patent describes a method to efficiently update dummy metal after a design change. Instead of re-running the entire dummy fill process, the method checks to see if any pre-existing dummy metal objects now intersect with new or moved design objects and deletes only those that do (Compl. ¶23; ’803 Patent, Abstract).
  • Asserted Claims: Claims 1-22 are implicated (Compl. ¶103).
  • Accused Features: The accused processes involve using Siemens' EDA tools to, after a design change, check for and delete intersecting dummy metal objects "thereby avoiding having to rerun the dummy fill tool" (Compl. ¶103).

U.S. Patent No. 6,436,807 - "Method for Making an Interconnect Layer and a Semiconductor Device Including the Same"

Issued August 20, 2002

  • Technology Synopsis: This patent aims to achieve uniform planarization during manufacturing by adding dummy fill features. The invention's approach is to determine the size and placement of dummy fill based on the "dielectric layer deposition bias"—how the insulating material builds up over existing features—to ensure a uniform final density (Compl. ¶25; ’807 Patent, Abstract).
  • Asserted Claims: Claims 1-18 are implicated (Compl. ¶107).
  • Accused Features: The accused processes involve using Siemens' EDA tools to add dummy fill features where the feature dimension is defined based on a dielectric layer deposition bias (Compl. ¶107).

U.S. Patent No. 7,149,989 - "Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design"

Issued December 12, 2006

  • Technology Synopsis: The patent addresses the problem of validating a chip design early without the long run times of a full rule check. The solution is to generate a "specific rule deck" that contains only a subset of rules from the main deck, targeted at identifying specific, high-priority errors like "texted metal short circuits" (Compl. ¶31; ’989 Patent, Abstract).
  • Asserted Claims: Claims 1-12 are implicated (Compl. ¶111).
  • Accused Features: The accused processes involve using Siemens' EDA tools to "generat[e] a specific rule deck from the physical design rule deck" to perform targeted checks (Compl. ¶111).

III. The Accused Instrumentality

Product Identification

The complaint identifies Plaintiff’s Electronic Design Automation (EDA) software products, specifically naming the "Calibre physical verification software product," as the accused instrumentalities (Compl. ¶3, ¶10).

Functionality and Market Context

The complaint describes these tools as a "complete integrated circuit verification and design for manufacturing optimization EDA platform" (Compl. ¶3). The infringement allegations are not based on the software itself being an infringing device, but on the methods performed by Plaintiff's customers when using the software to design and verify semiconductor chips (Compl. ¶13, ¶39). The complaint frames the use of these EDA tools by customers as being at the "heart of various BSLLC's infringement allegations" (Compl. ¶10). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

’259 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for inserting dummy metal into a circuit design... comprising: (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions; The complaint acknowledges that EDA tools identify empty areas for metal fill as a general function but contests the specific method alleged by Defendant (Compl. ¶91). ¶91 col. 2:29-32
and (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets. Plaintiff explicitly denies that its EDA design tools perform this function, stating they "at least do not 'prioritiz[e] the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last...'" (Compl. ¶91). This forms the core of the non-infringement argument. ¶91 col. 2:32-37

’626 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; Plaintiff asserts that its EDA tools, when used by customers, "at least do not 'create[e] at least one window ... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design'" (Compl. ¶95). This is a direct denial of the claimed functionality. ¶95 col. 8:59-64
performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; Plaintiff denies that its tools perform this step, stating they do not "'perform[] an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window'" (Compl. ¶95). ¶95 col. 9:1-4

Identified Points of Contention

  • Functional Questions: For all asserted patents, the central dispute appears to be one of technical operation. The complaint consistently denies that Plaintiff's software performs the specific, detailed steps required by the claims. For the ’259 patent, the question is whether the software's fill algorithm performs the specific "fill last" prioritization for clock-net-adjacent regions (Compl. ¶91). For the ’626 patent, the question is whether the software implements an ECO by creating a bounded "window" and performing "incremental routing" strictly within it (Compl. ¶95). The resolution will depend on evidence of how the accused software actually functions.
  • Scope Questions: A potential point of contention for the ’626 patent is the scope of "creating at least one window." The court may need to determine if this requires a specific user- or tool-defined bounding box as described in the patent's embodiments, or if it could more broadly cover any process that computationally isolates a design sub-region for localized changes.

V. Key Claim Terms for Construction

  • Term from the ’259 Patent: "prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last"

    • Context and Importance: This functional limitation is the core of the invention claimed in the ’259 patent and the central point of the infringement dispute. The case for this patent will likely turn on whether the accused software's operation falls within the scope of this phrase. Practitioners may focus on this term because Plaintiff's non-infringement position is a direct denial that its tools perform this specific prioritization (Compl. ¶91).
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A party might argue the claim language is result-oriented and covers any algorithm that, in effect, delays filling near clock nets relative to other regions. The summary of the invention describes the goal as minimizing timing impact, which could support a focus on the outcome rather than the precise method (’259 Patent, col. 2:44-47).
      • Evidence for a Narrower Interpretation: The detailed description and figures disclose a specific implementation where a "timing factor" is calculated for each region based on clock net width and criticality, a list is sorted by this factor, and metal is inserted in that order (’259 Patent, Fig. 5; col. 5:6-64). A party may argue the claim should be limited to this disclosed algorithm or a structurally equivalent one.

  • Term from the ’626 Patent: "creating at least one window"

    • Context and Importance: This term defines the essential first step of the patented method for handling ECOs. Infringement depends on whether the accused tools perform an operation that meets this definition.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent states the goal is to realize a "significant savings in the resources required" by operating on a small fraction of the design (’626 Patent, col. 3:15-20). This could support interpreting "creating... a window" to mean any method of computationally isolating a sub-region for processing, regardless of the specific technique used.
      • Evidence for a Narrower Interpretation: The specification discloses a detailed process for creating the window that involves identifying changed port instances, calculating bounding boxes around them, and merging overlapping boxes (’626 Patent, Fig. 3; col. 4:56-col. 5:12). A party could argue the claim term should be construed to require this specific bounding-box-based methodology.

VI. Other Allegations

  • Indirect Infringement: The entire declaratory judgment action is premised on allegations of indirect infringement. The complaint states that Defendant's lawsuits against Plaintiff's customers are "predicated on the Customers' use of Siemens' EDA design tools" (Compl. ¶12). Defendant’s theory is that the customers are direct infringers, which would make Plaintiff, as the supplier of the tools used to perform the patented methods, a potential contributory or induced infringer (Compl. ¶¶ 40, 52, 57).
  • Willful Infringement: The complaint notes that in the underlying customer lawsuits, Defendant seeks "enhanced damages" (Compl. ¶¶ 41, 53, 62), which is relief available for willful infringement. The basis for willfulness against the customers would likely be their alleged knowledge of the patents, which arises from Defendant's widespread litigation and licensing campaign.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue for the majority of the patents-in-suit will be one of functional operation: As a matter of technical fact, does the accused Siemens EDA software perform the specific, often multi-step, algorithmic processes recited in the independent claims—such as the "fill last" prioritization of the ’259 patent or the "windowed" incremental routing of the ’626 patent? The case is built on Plaintiff's assertion that its tools do not have this functionality.
  • A key threshold issue for the ’807 patent is one of contract and license: Does the 2001 license agreement between Siemens AG and Lucent Technologies cover the ’807 patent, which was assigned to the Lucent-related entity Agere Systems, and does that license protect the plaintiff, Siemens Industry Software Inc.? A finding of a valid license would render the infringement analysis for this patent moot.
  • Finally, the case will present a question of claim scope versus functionality: If the accused software achieves results similar to the patents (e.g., managing dummy fill or processing design changes efficiently) but through different technical means, the court will have to decide whether the claims are broad enough to cover the software's functionality or if they are limited to the specific embodiments and methods disclosed in the patent specifications.