Cedar Lane Tech Inc v. Opticon Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Opticon Inc. (Delaware)
  • Plaintiff’s Counsel: Napoli Shkolnik LLC
• Case Identification: 1:22-cv-01627, D. Del., 12/23/2022
• Venue Allegations: Venue is alleged to be proper as Defendant is incorporated in Delaware, maintains an established place of business in the district, and has allegedly committed acts of patent infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s products infringe three patents related to methods and modules for interfacing image sensors with data compression and processing systems.
• Technical Context: The technology concerns efficient data transfer and management between an image sensor and a host processor, a critical function in devices like digital cameras and scanners to reduce cost and complexity.
• Key Procedural History: The complaint does not specify any prior litigation or inter partes review proceedings. U.S. Patent No. 8,537,242 is a divisional of the application that matured into U.S. Patent No. 6,972,790 and is subject to a terminal disclaimer.

Case Timeline

Date	Event
1999-06-01	Priority Date for U.S. Patent No. 6,473,527
2000-01-21	Priority Date for U.S. Patent Nos. 6,972,790 and 8,537,242
2002-10-29	U.S. Patent No. 6,473,527 Issued
2005-12-06	U.S. Patent No. 6,972,790 Issued
2013-09-17	U.S. Patent No. 8,537,242 Issued
2022-12-23	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," issued October 29, 2002

The Invention Explained

• Problem Addressed: The patent’s background describes how conventional systems for JPEG image compression required an extra, external memory device (e.g., RAM) to sit between the analog-to-digital (A/D) converter and the JPEG compression chip. This was necessary to buffer image data and reformat it from a line-by-line stream into the block format (e.g., 8x8 pixels) that the JPEG algorithm requires, adding cost and complexity to the system. (’527 Patent, col. 1:35-57).
• The Patented Solution: The invention proposes an interface module that contains its own internal memory. This module reads a specific number of image lines (e.g., eight lines) from the A/D converter, stores them, and then provides correctly sized image blocks (e.g., 8x8 pixels) directly to the JPEG compression device. This integrated memory management obviates the need for the separate, external RAM buffer previously required. (’527 Patent, Abstract; col. 2:48-61; Fig. 2).
• Technical Importance: This design reduced the component count, cost, and complexity of image processing hardware such as digital scanners. (’527 Patent, col. 2:21-24).

Key Claims at a Glance

• The complaint asserts "Exemplary '527 Patent Claims" by reference to an exhibit not provided with the complaint (Compl. ¶15). Independent claim 1 is representative.
• Independent Claim 1 recites a module comprising:
  • "read control means" for sequentially reading a "predetermined number of image lines" from an A/D converter and generating a control signal.
  • "memory means" for storing those image lines, with a capacity matching the number of lines in the JPEG device’s built-in memory.
  • "output control means" that responds to the control signal by "sequentially reading an image block" from the memory means and forwarding it to the JPEG device’s built-in memory.
• The complaint alleges infringement of "one or more claims," reserving the right to assert dependent claims (Compl. ¶13).

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," issued December 6, 2005

The Invention Explained

• Problem Addressed: The patent identifies an incompatibility between the continuous, "video style output" of CMOS image sensors and the random-access data interfaces of commercial microprocessors. Bridging this gap required "additional glue logic," which diminished the cost and integration benefits of using CMOS technology. (’790 Patent, col. 1:37-58).
• The Patented Solution: The invention describes an interface, preferably integrated on the same semiconductor die as the image sensor, that acts as an intelligent buffer. It uses an internal memory (such as a first-in-first-out, or FIFO, buffer) to receive image data at the sensor's clock rate. The interface then signals the host processor (e.g., via an interrupt) when a certain amount of data has accumulated, allowing the processor to read the data from the buffer at its own, different rate. (’790 Patent, Abstract; col. 2:4-14).
• Technical Importance: By integrating the data-rate-matching and signaling functions onto the sensor chip, the invention facilitates a "system-on-a-chip" design, reducing the size, cost, and power consumption of devices like digital cameras. (’790 Patent, col. 1:27-31).

Key Claims at a Glance

• The complaint asserts "Exemplary '790 Patent Claims" by reference to an exhibit not provided with the complaint (Compl. ¶24). Independent claim 1 is representative.
• Independent Claim 1 recites an interface comprising:
  • "a memory" for storing image data and clocking signals at a rate determined by the sensor.
  • "a signal generator" for generating a signal to the processor "in response to the quantity of data in the memory."
  • "a circuit" for controlling the transfer of data from the memory at a rate determined by the processor.
• The complaint alleges infringement of "one or more claims," reserving the right to assert dependent claims (Compl. ¶19).

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," issued September 17, 2013

Technology Synopsis

As a divisional of the application for the ’790 patent, this patent covers similar technology for interfacing an image sensor with a host system. The claims focus on an interface that uses a memory buffer to manage data flow and a bus arbitration system to gain control of the system bus, allowing the interface to transfer stored image data to the host system efficiently. (’242 Patent, Abstract; col. 2:10-24).

Asserted Claims

The complaint asserts "Exemplary '242 Patent Claims" by reference to an exhibit not provided with the complaint (Compl. ¶¶ 28, 33).

Accused Features

The complaint alleges that the "Exemplary Defendant Products" practice the claimed technology but does not identify specific product features corresponding to the claims (Compl. ¶33).

III. The Accused Instrumentality

Product Identification

The complaint refers generally to "Exemplary Defendant Products" without naming specific products, models, or services (Compl. ¶13).

Functionality and Market Context

The complaint alleges infringement by incorporating by reference claim chart exhibits that were not filed with the public complaint (Compl. ¶¶ 15-16, 24-25, 33-34). As a result, the complaint does not provide sufficient detail for analysis of the accused products' specific functionality, operation, or market context.

IV. Analysis of Infringement Allegations

The complaint alleges direct and indirect infringement but relies on external exhibits (Exhibits 4, 5, and 6), which were not provided, to detail its infringement theories (Compl. ¶¶ 15, 24, 33). The narrative theory is that Defendant’s products practice the claimed technology, satisfying all claim elements either literally or under the doctrine of equivalents (Compl. ¶¶ 13, 19, 28).

No probative visual evidence provided in complaint.

• Identified Points of Contention:
  • Scope Questions: The use of "means-plus-function" language in the ’527 patent (e.g., "read control means") raises the question of whether the accused products contain structures that are identical or equivalent to those specifically disclosed in the patent’s specification for performing the claimed functions (’527 Patent, col. 2:48-51). For the ’790 and '242 patents, a key scope question may be whether the accused interface is integrated "on the same die" as the image sensor, a feature central to the "system-on-a-chip" benefit described in the specification (’790 Patent, col. 2:25-31).
  • Technical Questions: For the ’527 Patent, a central technical question is whether the accused products achieve data formatting by reading a "predetermined number of image lines" into a buffer before creating output blocks, as claimed, or if they use a different technical approach. For the ’790 Patent, a key question is what evidence shows that the accused device’s processor signal is generated "in response to the quantity of data in the memory," as required, rather than being triggered by another event, such as a fixed timer.

V. Key Claim Terms for Construction

Term: "read control means" / "output control means" (’527 Patent, Claim 1)

Context and Importance

These terms are drafted in means-plus-function format under 35 U.S.C. § 112(f). Practitioners may focus on these terms because their scope is not their plain meaning but is instead limited to the specific structures disclosed in the specification for performing the recited functions, plus their equivalents. The infringement analysis for the ’527 patent will depend heavily on identifying these structures and comparing them to the accused devices.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The specification describes the functions of these means in general terms, such as "sequentially reading" image lines and "generating a control signal," which could support an argument that any logic circuit performing these functions is covered (’527 Patent, col. 3:1-17).
• Evidence for a Narrower Interpretation: The patent explicitly identifies the corresponding structure as "read control device 22" and "output control device 23" within the "interface module 21" shown in Figure 2. An argument for a narrower construction would limit the claims to this disclosed two-controller architecture and its equivalents (’527 Patent, col. 2:48-51; Fig. 2).

Term: "in response to the quantity of data in the memory" (’790 Patent, Claim 1)

Context and Importance

This phrase defines the condition that triggers the signal to the host processor. Practitioners may focus on this term because the infringement determination will hinge on whether the accused products' signaling mechanism is causally linked to the buffer's fill level, or if it is triggered by an unrelated event.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The summary of the invention states broadly that the signal is generated "in response to the quantity of data in the memory," which could be argued to cover any signaling that occurs after some non-zero amount of data has been stored (’790 Patent, col. 2:8-9).
• Evidence for a Narrower Interpretation: A specific embodiment discloses an "interrupt generator 48" that "compares the FIFO counter output Sc and the FIFO limit SL" and asserts an interrupt if the count is greater than or equal to the limit. This could support a narrower construction requiring a direct comparison between a data count and a predetermined threshold (’790 Patent, col. 6:11-15; Fig. 2).

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement of the ’790 and ’242 patents. The alleged basis for inducement is Defendant's distribution of "product literature and website materials" that instruct customers and end users to operate the accused products in a manner that infringes the patents (Compl. ¶¶ 22-23, 31-32).
• Willful Infringement: The complaint alleges that Defendant has had "Actual Knowledge" of the ’790 and ’242 patents since the date of service of the complaint (Compl. ¶¶ 21, 30). This allegation supports a claim for post-suit willful infringement. No allegations of pre-suit knowledge are made. The prayer for relief also requests that the case be declared "exceptional," which could entitle the plaintiff to attorneys' fees (Compl. ¶ J(i)).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of structural equivalence: For the ’527 patent, which uses means-plus-function claiming, the dispute will likely center on whether the architecture of the accused products is structurally equivalent to the specific "read control" and "output control" devices disclosed in the patent's specification, or if it constitutes a distinct, non-infringing design.
• A key evidentiary question for the ’790 and ’242 patents will be one of functional causality: Does the evidence show that the accused interface generates its signal to the host processor specifically "in response to the quantity of data in the memory," as claimed, or is the signal triggered by a different, non-infringing condition, such as the completion of a line scan or a simple timer?
• A third pivotal question will concern physical integration: As the asserted patents emphasize the benefits of a "system-on-a-chip" design, a factual dispute may arise over whether the accused products' interface circuitry is integrated "on the same die" as the image sensor, a feature described in the patents and recited in certain dependent claims.