Cedar Lane Tech Inc v. Raytheon Tech Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Raytheon Technologies Corporation (Delaware)
  • Plaintiff’s Counsel: Napoli Shkolnik LLC
• Case Identification: 1:22-cv-01628, D. Del., 12/23/2022
• Venue Allegations: Venue is asserted based on Defendant's incorporation in Delaware, its established place of business within the district, and alleged acts of infringement committed in the district.
• Core Dispute: Plaintiff alleges that Defendant’s unspecified products infringe a patent related to a host interface for managing data transfer from an imaging array to a processor system.
• Technical Context: The technology addresses the challenge of efficiently transferring data from a high-rate image sensor to a host processor, a fundamental issue in digital camera and imaging system design.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

• Patent Identification: U.S. Patent No. 6,972,790, “Host interface for imaging arrays,” issued December 6, 2005.

U.S. Patent No. 6,972,790 - “Host interface for imaging arrays”

The Invention Explained

• Problem Addressed: The patent's background section describes a technical incompatibility between the continuous, video-style data stream produced by integrated circuit (IC) image sensors and the random-access data interface of commercial microprocessors. This mismatch historically required additional "glue logic," diminishing the cost and integration benefits of CMOS imaging technology ('790 Patent, col. 1:47-60).
• The Patented Solution: The invention proposes an interface, preferably integrated onto the same die as the image sensor, that acts as an intermediary. It uses a memory (such as a FIFO buffer) to receive and store image data at the sensor's rate. The interface then signals the host processor when a certain quantity of data is available and facilitates the transfer of that data to the processor at a rate determined by the processor, not the sensor. This decouples the two systems, allowing each to operate more efficiently ('790 Patent, Abstract; col. 2:4-14, Fig. 1).
• Technical Importance: This approach facilitates the creation of more highly integrated "system-on-a-chip" (SoC) imaging devices by incorporating necessary interface logic onto the same substrate as the sensor, a key benefit of CMOS technology ('790 Patent, col. 1:27-30).

Key Claims at a Glance

• The complaint asserts "one or more claims" without specifying them (Compl. ¶11). Independent claim 1 is representative of the core invention.
• Independent Claim 1 of the ’790 Patent recites:
  • An interface for receiving data from an image sensor and transferring it to a processor system.
  • A memory for storing imaging array data and clocking signals at a rate determined by the clocking signals.
  • A signal generator for generating a signal for the processor system "in response to the quantity of data in the memory."
  • A circuit for controlling the data transfer from the memory "at a rate determined by the processor system."
• The complaint reserves the right to assert additional claims, which may include other independent claims (e.g., claim 15) or dependent claims (Compl. ¶11).

III. The Accused Instrumentality

Product Identification

The complaint alleges infringement by "Exemplary Defendant Products" that are identified in charts within Exhibit 2 (Compl. ¶11, ¶16). However, Exhibit 2 was not filed with the public version of the complaint.

Functionality and Market Context

The complaint does not provide sufficient detail for analysis of the accused products' specific functionality or market context, as this information is deferred to the unattached Exhibit 2 (Compl. ¶17).

IV. Analysis of Infringement Allegations

The complaint alleges that the "Exemplary Defendant Products practice the technology claimed by the '790 Patent" and that they "satisfy all elements of the Exemplary '790 Patent Claims" (Compl. ¶16). The specific factual basis for these allegations is contained in claim chart exhibits that were not provided with the complaint (Compl. ¶17). Therefore, a detailed element-by-element analysis is not possible from the available documents.

No probative visual evidence provided in complaint.

Identified Points of Contention

• Scope Questions: A central question may be whether the architecture of the accused products aligns with the specific structure claimed. For instance, the analysis may focus on whether the accused products contain a distinct "signal generator" that operates "in response to the quantity of data in the memory," as opposed to a more general-purpose data-ready flag or status register that is polled by software.
• Technical Questions: A likely point of dispute is whether the data transfer in the accused products occurs "at a rate determined by the processor system" as required by the claim. The defense may argue that the transfer rate is dictated by a system bus protocol or a DMA controller, not directly by the processor system in the manner contemplated by the patent.

V. Key Claim Terms for Construction

"in response to the quantity of data in the memory" (from claim 1)

• Context and Importance: This phrase defines the trigger for notifying the processor. Its construction is critical to determining whether the claim covers systems where the processor actively polls a memory status, versus systems with a dedicated hardware mechanism that automatically generates a signal (e.g., an interrupt) when a data-level threshold is met. Practitioners may focus on this term to distinguish between hardware-driven and software-driven data management schemes.
• Intrinsic Evidence for a Broader Interpretation: The claim language itself is general. The summary of the invention also broadly describes the signal generator acting "in response to the quantity of data" without specifying the mechanism ('790 Patent, col. 2:7-10).
• Intrinsic Evidence for a Narrower Interpretation: A specific embodiment describes an "interrupt generator 48" that explicitly "compares the FIFO counter output Sc and the FIFO limit Sₗ" to generate the signal ('790 Patent, col. 6:11-15). A party could argue this embodiment limits the term's scope to a direct, hardware-based comparison.

"at a rate determined by the processor system" (from claim 1)

• Context and Importance: This limitation defines the control over data outflow from the interface's buffer memory, distinguishing the invention from systems where the sensor's clock dictates the end-to-end data rate. The construction will determine if modern bus-mastering or DMA-based systems, where the processor initiates a transfer but a separate controller manages the rate, fall within the claim's scope.
• Intrinsic Evidence for a Broader Interpretation: The phrase could be interpreted to mean any transfer whose initiation and control originates from the processor side of the system, as opposed to the sensor side.
• Intrinsic Evidence for a Narrower Interpretation: The detailed description explains that the CPU accesses the interface through a "Chip Command Decoder 45" to assert read commands, which in turn causes a "FIFO Read Control 47" to generate read signals ('790 Patent, col. 5:52-63). This suggests a direct, command-level control by the processor, which could support a narrower interpretation than a fire-and-forget DMA transfer.

VI. Other Allegations

Indirect Infringement

The complaint alleges induced infringement, stating that Defendant sells the accused products to customers and distributes "product literature and website materials" that instruct end users on how to use the products in an infringing manner (Compl. ¶14, ¶15).

Willful Infringement

The complaint alleges that service of the complaint itself provides Defendant with "actual knowledge of infringement" (Compl. ¶13). It further alleges that Defendant "continues to make, use, test, sell, offer for sale, market, and/or import" the products despite this knowledge, which forms the basis for a claim of post-suit willful infringement (Compl. ¶14).

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be one of evidentiary sufficiency: as the complaint's infringement contentions are contained entirely within an unattached exhibit, a key initial question is what factual evidence Plaintiff will produce to show that the accused products contain the specific four-part architecture recited in independent claim 1.
• The case may also hinge on a question of technological scope: can the claim term "at a rate determined by the processor system," which is rooted in the context of direct CPU-controlled reads described in the patent, be construed to cover modern, high-speed data transfer protocols where a bus master or DMA controller, rather than the CPU itself, directly manages the data transfer rate?