DCT
1:23-cv-00006
NovaSparks Inc v. Exegy Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: NovaSparks, Inc. (Massachusetts)
- Defendant: Exegy Inc. (Delaware)
- Plaintiff’s Counsel: Greenberg Traurig, LLP
- Case Identification: 1:23-cv-00006, D. Del., 01/03/2023
- Venue Allegations: Venue is alleged to be proper in the District of Delaware because Defendant is a Delaware corporation and resides in the district for venue purposes.
- Core Dispute: Plaintiff alleges that Defendant’s FPGA-based financial data processing products, used for low-latency trading, infringe a patent related to a specialized hardware matrix architecture.
- Technical Context: The technology at issue involves the use of Field-Programmable Gate Arrays (FPGAs) to accelerate the processing of high-volume financial market data, where sub-microsecond latency can provide a significant competitive advantage in trading.
- Key Procedural History: The complaint alleges that Defendant Exegy acquired a company named Enyx, a developer of FPGA-based trading products, in May 2022. This acquisition allegedly brought the accused products under Defendant's control.
Case Timeline
| Date | Event |
|---|---|
| 2012-02-16 | '931 Patent Earliest Priority Date (Prov. App. 61/599,856) |
| 2018-02-27 | '931 Patent Issue Date |
| 2022-05-XX | Exegy acquires Enyx and its associated products |
| 2023-01-03 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 9,904,931 - FPGA matrix architecture, Issued Feb. 27, 2018
The Invention Explained
- Problem Addressed: The patent describes the challenge of processing massive volumes of financial market data with minimal delay. Conventional systems using standard CPUs struggle with latency, particularly during "micro-bursts" of high data traffic, which can lead to performance bottlenecks. (’931 Patent, col. 1:50-68).
- The Patented Solution: The invention proposes a system architecture based on a "matrix" of interconnected Field-Programmable Gate Array (FPGA) nodes. These nodes are linked by high-speed, low-latency connections, allowing for deterministic, parallel processing of data feeds from various sources. This hardware-centric approach is designed to maintain consistent, sub-microsecond processing latencies even under burst conditions, inverting the conventional paradigm where FPGAs act as secondary co-processors to a primary CPU. (’931 Patent, col. 2:11-29; col. 11:58-65). Figure 4 illustrates a system where dedicated FPGA nodes (e.g., NASDAQ Node, BATS US Node) process feeds from specific exchanges before data is aggregated and sent to trading servers. (’931 Patent, Fig. 4).
- Technical Importance: In the field of high-frequency trading, processing speed is paramount, and this architecture claims to provide a deterministic, ultra-low latency platform for handling market data. (’931 Patent, col. 1:24-29).
Key Claims at a Glance
- The complaint asserts at least independent claim 1. (Compl. ¶25).
- Independent Claim 1 recites a network appliance comprising:
- A matrix of at least three FPGA nodes, each with memory and I/O.
- Each of the three FPGA nodes includes at least two physical links to other nodes in the matrix, with the links being low latency and high bandwidth.
- At least one circuit board housing one or more of the FPGA nodes.
- At least one external link connected to the matrix for receiving high-volume, real-time market data feeds characterized by "data burst conditions."
- At least one FPGA node that receives these feeds and extracts raw market data for processing.
- "Another FPGA node" configured to build real-time order books from the raw market data.
- At least one of the FPGA nodes configured to transmit messages, including the processed market data, to a plurality of trading servers for trade analysis and execution.
- The complaint alleges infringement of "one or more claims" and reserves the right to augment its allegations. (Compl. ¶¶22, 42).
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are Defendant Exegy’s ticker plants, "nxFeed" feed handlers, and "nxAccess" engine, collectively referred to as the "Accused Products." (Compl. ¶15). These products allegedly came under Exegy's control after its acquisition of Enyx. (Compl. ¶¶17-18).
Functionality and Market Context
The complaint alleges that the Accused Products are network appliances designed to process high-volume market data feeds for algorithmic trading. (Compl. ¶28). The "nxFeed" product is described as a feed handler that uses FPGAs to "arbitrate, decode, normalize and build order books," processing data feeds from exchanges and making them available via a normalized API. (Compl. ¶¶31, 38). The complaint alleges these components are designed to be installed and operated together in an "FPGA server" to form a low-latency trading system. (Compl. ¶19).
IV. Analysis of Infringement Allegations
The complaint alleges that an appliance comprising multiple "nxFeed" handlers and a ticker plant, operating within an FPGA server, infringes at least Claim 1 of the ’931 patent. (Compl. ¶¶27-28). The complaint includes a diagram from Defendant's marketing materials depicting three "nxFeed" handlers receiving data from "Exchanges" and connecting via a PCIe bus to a "Ticker Plant" within an "FPGA SERVER." (Compl. ¶28, p. 8).
'931 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a matrix of at least three FPGA nodes wherein each FPGA node includes respective memory, and I/O | Defendant's appliance allegedly uses at least three "nxFeed" feed handlers and a ticker plant, which are alleged to be FPGA nodes with memory and I/O. | ¶¶30-32 | col. 16:28-30 |
| wherein each of the at least three FPGA nodes includes at least two physical links, the at least two physical links each being connected to respective ones of the other nodes in the matrix each of the at least two physical links comprises a low latency high bandwidth connection | The "nxFeed" handlers are allegedly connected to each other and to the ticker plant via internal connections and a low latency, high bandwidth PCIe bus within the FPGA server. | ¶¶33-34 | col. 16:31-36 |
| at least a first circuit board housing one or more FPGA nodes of the matrix of FPGA nodes | The "nxFeed" feed handler is allegedly deployed on a network interface card (NIC), which comprises a circuit board. | ¶35 | col. 16:37-39 |
| at least one additional external link connected to the matrix of FPGA nodes, wherein the external link is directly connected to one or more high volume real-time market data feeds...wherein at least one node in the matrix of FPGA nodes receives the one or more high-volume real-time market data feeds to extract raw market data... | Each "nxFeed" feed handler is allegedly connected to external market data feeds from exchanges and has a node to receive the feeds and extract raw market data. | ¶¶36-37 | col. 16:40-49 |
| the another FPGA node configured to build in real-time one or more order books associated with a plurality of financial instruments... | Nodes within the "nxFeed" feed handlers are alleged to "arbitrate, decode, normalize and build order books." | ¶38 | col. 16:50-55 |
| wherein at least one of three FPGA nodes includes at least one additional physical link and is configured to transmit messages to a plurality of trading servers... | The appliance is allegedly designed for algorithmic trading, with "nxFeed" integrating with the "nxAccess" trading engine to transmit processed market data for trade execution. | ¶¶39-40 | col. 16:56-62 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the combination of separate products ("nxFeed" handlers and a "Ticker Plant") connected by a standard PCIe bus constitutes a "matrix of...FPGA nodes" as that term is used in the patent. The defense may argue the term implies a more bespoke, integrated architecture than what is alleged.
- Technical Questions: The complaint relies heavily on marketing materials. A key factual question will be whether discovery reveals that the internal workings of the Accused Products perform the specific functions claimed. For instance, what evidence demonstrates that one FPGA node is specifically configured for "building...order books" while another is configured for "transmitting messages to...trading servers" in a manner that maps cleanly onto the claim's distinct functional limitations?
V. Key Claim Terms for Construction
The Term: "matrix of at least three FPGA nodes"
- Context and Importance: The definition of "matrix" is foundational to the infringement case. The plaintiff’s theory appears to treat a collection of distinct hardware components ("nxFeed" handlers, ticker plant) connected by a system bus as a "matrix." The viability of this theory depends on how broadly the term is construed. Practitioners may focus on this term because its construction could determine whether a standard server architecture with multiple FPGA cards can meet the limitation.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent specification describes the invention as a "matrix of FPGA nodes" without tightly defining the term, and states the nodes can be "linked through raw binary interconnections" or "different connections can be configured as part of the matrix." (’931 Patent, col. 2:44-46). This language may support a flexible definition that includes various interconnection types.
- Evidence for a Narrower Interpretation: The specification also discusses "point to point connection[s]" and a proprietary "FASTLink" protocol, and emphasizes a departure from conventional architectures. (’931 Patent, col. 7:12-16; col. 12:50-59). This could support an argument that "matrix" requires a more specific, non-standard interconnection fabric than a general-purpose PCIe bus.
The Term: "low latency high bandwidth connection"
- Context and Importance: This term's meaning is critical for determining if the alleged PCIe bus connection between the FPGA nodes satisfies the claim. The term is relative and its construction will likely involve expert testimony regarding what a person of ordinary skill in the art would have understood "low latency" and "high bandwidth" to mean in this context at the time of the invention.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not set specific numerical thresholds for latency or bandwidth in the claims. It does, however, provide a performance target of "less than 1 microsecond" for the overall system, which could serve as a benchmark. (’931 Patent, col. 2:24-26).
- Evidence for a Narrower Interpretation: The specification contrasts the invention's connections with PCIe, noting that its "FASTLink" provides "lower latency than, for example, a PCIe link, which would require each data transfer to be setup." (’931 Patent, col. 8:49-53). This passage could be used to argue that a standard PCIe link does not meet the "low latency" requirement as envisioned by the inventor.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement, stating that Defendant provides the Accused Products with marketing materials and instructions that encourage and aid customers in using the products in an infringing manner. (Compl. ¶¶45-46). The complaint also pleads contributory infringement, alleging the Accused Products are especially made for infringing use and are not staple articles of commerce suitable for substantial non-infringing use. (Compl. ¶50).
- Willful Infringement: Willfulness is alleged based on Defendant’s awareness of the infringement "at least as a result of the filing of this Complaint." (Compl. ¶48). This is a claim for post-suit willfulness.
VII. Analyst’s Conclusion: Key Questions for the Case
The resolution of this dispute may turn on the following central questions:
A core issue will be one of definitional scope: Can the term "matrix of ... FPGA nodes," as described in a patent that contrasts its invention with conventional systems, be construed to cover an assembly of separate commercial products ("nxFeed", "Ticker Plant") communicating over a standard PCIe bus within a server?
A second key issue will be one of technical mapping: Assuming a favorable claim construction for the plaintiff, does the evidence show that the Accused Products' distributed architecture assigns the discrete functions required by Claim 1 (e.g., receiving data, building order books, transmitting to servers) to distinct FPGA nodes in the specific manner recited by the patent's limitations?