DCT

1:23-cv-01122

Samsung Electronics Co Ltd v. Netlist Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:23-cv-01122, D. Del., 10/09/2023
  • Venue Allegations: Venue is alleged to be proper because Defendant is a Delaware corporation subject to personal jurisdiction, and the action arises from Defendant’s assertions in a related case within the district.
  • Core Dispute: Plaintiff seeks a declaratory judgment that its memory modules do not infringe Defendant's patent related to memory module signaling and, alternatively, alleges Defendant breached its contractual obligations to license the patent on reasonable and non-discriminatory (RAND) terms.
  • Technical Context: The technology concerns high-performance memory modules (DIMMs) for servers and computers, specifically a method for a module to signal its status to a system controller during initialization procedures.
  • Key Procedural History: This declaratory judgment action follows extensive litigation between the parties. The patent-in-suit is a continuation of two related patents previously asserted by Netlist against Samsung. Those two patents were recently invalidated in their entirety by the Patent Trial and Appeal Board (PTAB) in proceedings initiated by Samsung, and Netlist’s attempt to appeal those decisions was rejected as untimely. The complaint also alleges a broader dispute over a 2015 licensing agreement and Netlist's alleged obligations to license patents essential to the JEDEC memory standards on RAND terms.

Case Timeline

Date Event
2009-06-12 Earliest Priority Date for U.S. Patent No. 11,386,024
2015-11-12 Samsung and Netlist enter into Joint Development and License Agreement
2020-07-15 Netlist sends letter purporting to terminate the license agreement
2021-10-15 Samsung files IPRs against parent patents to the '024 patent
2022-07-12 U.S. Patent No. 11,386,024 issues
2023-05-09 PTAB issues Final Written Decisions invalidating all claims of parent patents
2023-10-09 Complaint for Declaratory Judgment filed by Samsung

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 11,386,024 - Memory Module Having an Open-Drain Output for Parity Error and for Training Sequences

  • Patent Identification: U.S. Patent No. 11,386,024, "Memory Module Having an Open-Drain Output for Parity Error and for Training Sequences," issued July 12, 2022 (’024 Patent).

The Invention Explained

  • Problem Addressed: The patent asserts that in computer systems, there was "no existing method of handshaking between the MCH (e.g., system memory controller) and a memory subsystem (e.g., memory module) during initialization" (’024 Patent, col. 3:40-43). This forces the system controller to perform "blind execution," often inserting pre-set idle periods while waiting for a memory module to complete an internal task, which is inefficient, especially for advanced memory types like Load-Reduced DIMMs (LR-DIMMs) where the controller may hand off initialization tasks to the module itself (’024 Patent, col. 4:28-65; Compl. ¶65).
  • The Patented Solution: The invention provides a handshake mechanism where the memory module can actively notify the system controller of its status (’024 Patent, col. 4:48-55). It achieves this by using a single output pin—specifically an open-drain output that may also function as a standard error-out pin—for a dual purpose. During normal operation, the pin signals a parity error. During initialization, however, the same pin is used to send a "notification signal" to indicate the status of internal "training sequences," such as when they are complete (’024 Patent, Abstract, col. 9:1-14). As depicted in the patent's Figure 1, this allows multiple memory modules tied to a common bus to signal the system controller only when all modules have finished their respective tasks (Compl. ¶¶66-68).
  • Technical Importance: This method allows a system controller to avoid inefficient, fixed-duration waiting periods and receive immediate confirmation that a module-specific task is complete, thereby speeding up the overall system initialization process (’024 Patent, col. 4:40-51).

Key Claims at a Glance

  • The complaint identifies independent claims 1, 10, and 19 as being at issue (Compl. ¶105).
  • The essential elements of independent claim 1 are:
    • A memory module operable with a memory controller of a host system, comprising: a printed circuit board (PCB) with edge connections, including first, second, and an additional "error edge connection."
    • A module controller on the PCB configured to receive address/control signals.
    • Dynamic random access memory (DRAM) elements on the PCB.
    • The module controller includes a transistor with an "open drain coupled to the error edge connection."
    • The module controller is configured to apply a first signal to the transistor gate to indicate a parity error during a normal memory read or write operation.
    • The module controller is "further configured to apply a second signal related to one or more training sequences to the gate of the transistor when the memory module performs operations associated with the one or more training sequences" and the DRAM is not being accessed for normal operations.
  • The complaint notes that dependent claims 2-9, 11-18, and 20 are also not infringed (Compl. ¶109).

III. The Accused Instrumentality

Product Identification

  • Samsung’s LRDIMM and RDIMM memory modules compliant with DDR4 standards, and its RDIMM memory modules compliant with DDR5 standards (collectively, the "Samsung Memory Modules") (Compl. ¶61).

Functionality and Market Context

  • The accused products are industry-standard memory modules used in a wide range of computer systems (Compl. ¶25, ¶61). The complaint alleges that Netlist’s infringement theory is premised on the idea that compliance with certain JEDEC standards (e.g., DDR4, DDR5) and use of features like "Clock-to-CA training" necessarily results in infringement of the ’024 Patent family (Compl. ¶58, ¶69). The specific accused functionality involves the use of the "ALERT_n" output pin during Clock-to-CA training to signal status to the system memory controller (Compl. ¶108).

IV. Analysis of Infringement Allegations

Samsung seeks a declaratory judgment of non-infringement. Its allegations focus on why the Samsung Memory Modules do not meet specific limitations of the ’024 Patent’s claims. The complaint includes Figure 1 from the patent, which illustrates a system with a memory controller (14) and multiple memory modules (10, 26) whose outputs are coupled to a common bus (32) to provide a notification signal (Compl. ¶66).

’024 Patent Infringement Allegations

Claim Element (from Independent Claim 1) Samsung's Alleged Non-Infringing Functionality Complaint Citation Patent Citation
a printed circuit board having edge connections that fit into a corresponding slot of the host system... The complaint alleges that the Samsung Memory Modules do not include the required "host system" or its "corresponding slot." ¶107 col. 15:18-24
wherein the module controller is further configured to apply a second signal related to one or more training sequences to the gate of the transistor when the memory module performs operations associated with the one or more training sequences... The complaint argues that the signal on the "ALERT_n" output pin of the accused modules during Clock-to-CA training is not the claimed "second signal." It further states this pin is "polled by the system memory controller," which it contends does not satisfy the claim requirements. ¶108 col. 16:39-49

Identified Points of Contention

  • Scope Questions: A central dispute concerns the scope of "host system." The case raises the question of whether a memory module sold alone can be found to infringe a claim that recites elements of the "host system" in which it operates, or if those elements must be considered part of the accused instrumentality itself.
  • Technical Questions: What evidence demonstrates that the accused "ALERT_n" signal is functionally distinct from the claimed "second signal"? The patent’s specification distinguishes between a "polling method" and its own "notifying method" (’024 Patent, col. 4:20-43). The key technical question is whether the accused modules' signaling, which the complaint alleges is "polled," is technically and legally equivalent to the "notifying" function required by the claims.

V. Key Claim Terms for Construction

The Term: "host system"

  • Context and Importance: Samsung's primary non-infringement argument is that its memory modules do not include the claimed "host system" or its "corresponding slot" (Compl. ¶107). The construction of this term is therefore critical. Practitioners may focus on this term because its definition could determine whether the claims cover a standalone memory module or require the entire computer system to be the infringing article.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The preamble of claim 1 describes "[a] memory module operable with a memory controller of a host system," which could suggest the host system is the environment for the module, not part of the claimed module itself (’024 Patent, col. 15:15-17).
    • Evidence for a Narrower Interpretation: The body of claim 1 recites "a corresponding slot of the host system," which Samsung argues requires the host system to be part of the claimed invention (Compl. ¶107). The patent consistently depicts the "host computer system 16" as containing, but being distinct from, the "memory module 10" (’024 Patent, Fig. 1), which may support an interpretation that the "host system" is an external element not supplied by the memory module manufacturer.

The Term: "apply a second signal related to one or more training sequences"

  • Context and Importance: This term defines the core inventive function. Samsung alleges its use of a "polled" "ALERT_n" pin does not meet this limitation (Compl. ¶108). The infringement analysis will depend on whether this claim language is broad enough to read on a polled signal or is limited to the "notifying" embodiment described in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim language itself does not explicitly require a specific signaling method (e.g., interrupt-driven) or forbid polling. An argument could be made that any signal that conveys the status of a training sequence is "related to" it.
    • Evidence for a Narrower Interpretation: The specification explicitly contrasts an inefficient "polling method" with the invention's "advantageous" "notifying method" (’024 Patent, col. 4:20-43). A court may determine this descriptive language limits the scope of "apply a... signal" to an active notification, excluding a passive state that is merely available for polling.

VI. Other Allegations

  • Indirect Infringement: Samsung seeks a declaration that it is not liable for indirect infringement under 35 U.S.C. § 271(b)-(c), in addition to its denial of direct infringement (Compl. ¶112).
  • Breach of Contract (RAND Obligations): As a separate count, Samsung alleges that Netlist is a member of the JEDEC standard-setting organization and is therefore contractually obligated to license any of its patents that are essential to a JEDEC standard on RAND terms (Compl. ¶¶83, 98). The complaint alleges that to the extent the ’024 patent is essential to the DDR4 or DDR5 standards, Netlist has breached this obligation by, among other things, seeking injunctive relief against users of standard-compliant products and failing to offer Samsung a license on RAND terms (Compl. ¶¶99, 101, 119).

VII. Analyst’s Conclusion: Key Questions for the Case

This case presents a multi-faceted dispute combining patent infringement with contract law related to standard-essential patents. The key questions for the court appear to be:

  • A core issue will be one of claim construction: Can the term "host system," recited in the claims, be interpreted to cover the standard computer environment in which Samsung's memory modules operate, or is it a required element of the infringing device that is absent from the accused products?
  • A key evidentiary question will be one of functional distinction: Does the accused memory modules' "polled" "ALERT_n" signal perform the same function as the claimed "second signal," particularly in light of the patent's explicit preference for a "notifying" method over a "polling" one?
  • A dispositive parallel issue will be one of contractual obligation: If the patent is found to be both infringed and valid, is it essential to the JEDEC standard? If so, has Netlist breached its RAND licensing commitments, which could preclude injunctive relief and cap potential damages?