Cedar Lane Tech Inc v. Amlogic Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: Amlogic, Inc. (Delaware)
  • Plaintiff’s Counsel: Phillips, McLaughlin & Hall, P.A.; Rabicoff Law LLC
• Case Identification: 1:23-cv-01242, D. Del., 10/31/2023
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because the Defendant is a Delaware corporation and has allegedly committed acts of patent infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant's semiconductor products infringe patents related to a host interface for imaging arrays.
• Technical Context: The technology concerns specialized interface circuitry designed to efficiently manage the data transfer between an image sensor and a host processor system, a key component in modern System-on-a-Chip (SoC) designs.
• Key Procedural History: The complaint notes that U.S. Patent No. 8,537,242 is a divisional of the application that resulted in U.S. Patent No. 6,972,790. No other significant procedural events, such as prior litigation or administrative proceedings, are mentioned in the complaint.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,972,790 - “Host interface for imaging arrays,” issued Dec. 6, 2005

The Invention Explained

• Problem Addressed: The patent’s background describes an incompatibility between the continuous, fixed-rate "video style output" of conventional IC image sensors and the random-access data interfaces of commercial microprocessors. This mismatch required additional "glue logic" to bridge the two, which undermined the cost and integration benefits of using CMOS technology for imaging systems (’790 Patent, col. 1:38-57).
• The Patented Solution: The invention proposes an interface, preferably integrated on the same semiconductor die as the image sensor, to act as an intermediary. This interface uses an on-chip memory, such as a First-In-First-Out (FIFO) buffer, to temporarily store data from the imaging array as it is generated. The interface then monitors the amount of data in the memory and, upon reaching a certain threshold, generates a signal (e.g., an interrupt) to the host processor, which can then read the buffered data at its own pace. (’790 Patent, Abstract; col. 2:4-14). This architecture decouples the sensor's rigid timing from the processor's operations, as illustrated in the system diagram of Figure 1 (’790 Patent, Fig. 1).
• Technical Importance: This design facilitates the creation of more highly integrated and cost-effective System-on-a-Chip (SoC) devices by eliminating the need for separate interface components between the image sensor and the processor (’790 Patent, col. 1:25-30, 63-67).

Key Claims at a Glance

• The complaint does not identify specific claims asserted from the ’790 Patent, instead referring to "Exemplary '790 Patent Claims" detailed in an exhibit not attached to the publicly filed complaint (Compl. ¶12, ¶14). Independent Claim 1 is representative of the core invention.
• Independent Claim 1 requires:
  • An interface for receiving data from an image sensor having an imaging array and a clock generator for transfer to a processor system comprising:
  • a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals;
  • a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory; and
  • a circuit for controlling the transfer of the data from the memory at a rate determined by the processor system.
• The complaint alleges infringement of "one or more claims" of the patent (Compl. ¶12).

U.S. Patent No. 8,537,242 - “Host interface for imaging arrays,” issued Sep. 17, 2013

The Invention Explained

• Problem Addressed: As a divisional of the ’790 Patent's application, the ’242 Patent addresses the same fundamental problem: the need for an efficient interface to manage the data flow between a constant-rate image sensor and a host processor, thereby avoiding complex and costly external "glue logic" (’242 Patent, col. 1:43-59).
• The Patented Solution: The ’242 Patent claims methods of processing imaging signals using a similar interface architecture. A key aspect detailed in certain claims is the interface’s ability to more autonomously manage data transfers. Instead of only interrupting the CPU, the interface can generate a "bus request signal" to a "bus arbitration unit", seeking direct control of the system bus to transfer the buffered image data to another location in memory, a process akin to Direct Memory Access (DMA). (’242 Patent, Abstract; col. 2:10-18). This bus arbitration-based approach is depicted in Figure 6 (’242 Patent, Fig. 6).
• Technical Importance: This method further enhances system efficiency by offloading data transfer tasks from the main CPU, freeing it to perform other computations while image data is moved in the background (’242 Patent, col. 6:33-40).

Key Claims at a Glance

• The complaint does not specify which claims of the ’242 Patent are asserted, referring to "Exemplary '242 Patent Claims" in an unattached exhibit (Compl. ¶18, ¶23). Independent claims 1 and 8 are representative of the different methods claimed.
• Independent Claim 1 is a method claim requiring steps of receiving and storing image data in a FIFO, updating a counter, comparing the count to a limit, and generating an "interrupt signal" for a processor.
• Independent Claim 8 is a method claim requiring similar initial steps but culminates in generating a "bus request signal" to a "bus arbitration unit" to gain access to an output bus for data transfer.
• The complaint alleges infringement of "one or more claims" of the patent (Compl. ¶18).

III. The Accused Instrumentality

Product Identification

• The complaint does not name any specific accused products in its main body. It refers generally to "Exemplary Defendant Products" that are identified and analyzed in claim charts provided as Exhibits 3 and 4 (Compl. ¶12, ¶23). As these exhibits were not included with the filed complaint, the specific instrumentalities at issue are not identified in the available documents.

Functionality and Market Context

• The complaint alleges that Defendant makes, uses, offers for sale, and imports the accused products (Compl. ¶12, ¶18). The functionality of these products is described only through the allegation that they "practice the technology claimed" and "satisfy all elements" of the asserted patent claims, as purportedly shown in the unattached exhibits (Compl. ¶14, ¶23). The complaint does not contain specific allegations regarding the products' market position or commercial importance.

IV. Analysis of Infringement Allegations

The complaint’s infringement allegations for both patents rely entirely on claim charts that were filed as exhibits but are not available for analysis in the main complaint document (Compl. ¶15, ¶24). The pleading states that these charts compare the "Exemplary... Patent Claims" to the "Exemplary Defendant Products" and demonstrate that the products satisfy all claim elements (Compl. ¶14, ¶23).

For the ’790 Patent, the complaint alleges direct infringement, including through internal testing by Defendant's employees (Compl. ¶12-13). For the ’242 Patent, the complaint alleges both direct infringement and induced infringement (Compl. ¶18, ¶22). The inducement theory is based on allegations that Defendant distributes "product literature and website materials" that instruct end users on how to use the accused products in an infringing manner (Compl. ¶21).

Without the accompanying claim chart exhibits, a detailed element-by-element analysis of the infringement allegations is not possible.

No probative visual evidence provided in complaint.

V. Key Claim Terms for Construction

’790 Patent: "a memory for storing imaging array data and clocking signals" (from Claim 1)

• Context and Importance: The precise scope of this limitation is critical. The dispute may center on whether the accused products' internal buffers store "clocking signals" in the manner required by the claim, or if they only store pixel data. Practitioners may focus on this term because a narrow interpretation could allow a defendant to design around the claim by arguing its memory architecture is different.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification suggests flexibility, stating the memory "may be a first-in first-out (FIFO) buffer or an addressable memory" (’790 Patent, col. 2:11-13). This could support an argument that the exact structure is not limiting.
  • Evidence for a Narrower Interpretation: Figure 5 depicts clock signals (CR, CF) being "bundled onto a single bus 51 for storage in the buffer 44" along with the array data (Da) (’790 Patent, col. 5:11-14). A party could argue this requires the literal storage of clock signal values, not merely using those signals to time the storage of pixel data.

’242 Patent: "bus request signal" (from Claim 8)

• Context and Importance: This term is central to the novelty of the method claimed in Claim 8, distinguishing it from simpler interrupt-based systems. The case may turn on whether the control signals used in the accused products qualify as a "bus request signal" sent to a "bus arbitration unit."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The term is not explicitly defined in the specification, which could support giving it a plain and ordinary meaning as understood in the field of computer architecture at the time. The patent states the interface "sends a bus request signal SBR to the bus arbitration unit 61" without further limiting the signal's specific protocol (’242 Patent, col. 6:33-36).
  • Evidence for a Narrower Interpretation: Figures 6 and 7 illustrate a specific architecture where a "bus request signal" (SBR) is sent to a distinct component labeled a "Bus Arbitration Unit" (61), which then returns an "arbitration acknowledgement signal" (SAA) (’242 Patent, Figs. 6, 7). A defendant could argue its integrated SoC architecture lacks these specific, discrete functional blocks and therefore does not practice the claimed method.

VI. Other Allegations

• Indirect Infringement: This is alleged for the ’242 Patent only. The complaint alleges inducement based on Defendant’s distribution of "product literature and website materials," which purportedly instruct customers and end users to operate the accused products in a manner that directly infringes the patent (Compl. ¶21-22).
• Willful Infringement: The complaint does not use the term "willful." However, for the ’242 Patent, it explicitly pleads "Actual Knowledge of Infringement" arising from the date of service of the complaint and alleges that "Defendant continues to make, use, test, sell, offer for sale, market, and/or import" infringing products despite this knowledge (Compl. ¶20-21). These allegations form a basis for a claim of post-suit willful infringement. No allegations of pre-suit knowledge are made.

VII. Analyst’s Conclusion: Key Questions for the Case

• A primary issue will be one of evidentiary sufficiency. The complaint's infringement contentions are wholly contained within unattached exhibits. A threshold question for the litigation will be whether the evidence, once revealed, can substantiate the conclusory allegation that specific features of Amlogic's products map onto the patent's claim elements.
• The case will also involve a core question of claim construction and technical scope. The dispute will likely focus on whether key terms such as "a memory for storing... clocking signals" (’790 Patent) and "bus request signal" (’242 Patent) should be interpreted broadly according to their function or narrowly based on the specific circuit diagrams shown in the patent embodiments.
• Ultimately, the infringement analysis may turn on a question of functional operation. A central dispute will be whether the accused Amlogic interfaces, operating within modern and complex SoC environments, perform the specific, discrete steps recited in the claims—such as generating a formal bus request in response to a FIFO fill level—or if they manage data flow using a technically distinct methodology not covered by the patents.