DCT

1:25-cv-00359

Synopsys Inc v. Real Intent Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00359, D. Del., 03/21/2025
  • Venue Allegations: Plaintiff alleges venue is proper in the District of Delaware primarily because Defendant is a Delaware corporation. The complaint further alleges Defendant has purposefully availed itself of the privileges of conducting business in Delaware by regularly soliciting business, offering infringing products for sale through its websites, and entering into contracts with customers under Delaware law.
  • Core Dispute: Plaintiff alleges that Defendant’s electronic design automation (EDA) software for static verification infringes six patents related to analyzing and debugging complex integrated circuit designs.
  • Technical Context: The technology is in the field of electronic design automation (EDA), which provides software tools for designing and verifying semiconductors before the costly manufacturing process.
  • Key Procedural History: The complaint alleges that Defendant had pre-suit knowledge of several patents-in-suit. Specifically, it alleges that U.S. Patent Nos. 9,792,394 and 10,289,773 were cited by a patent examiner during the prosecution of Defendant’s own patent applications, and that Defendant itself cited U.S. Patent No. 8,650,513 in one of its patent applications. The complaint also alleges general knowledge of Plaintiff's patent portfolio since approximately 2018.

Case Timeline

Date Event
2010-09-20 U.S. Patent No. 8,650,513 Priority Date
2011-03-09 U.S. Patent No. 8,607,173 Priority Date
2011-04-11 U.S. Patent No. 8,359,560 Priority Date
2013-10-31 U.S. Patent No. 9,529,948 Priority Date
2013-12-10 U.S. Patent No. 8,607,173 Issued
2013-12-10 U.S. Patent No. 9,529,948 Issued
2014-02-11 U.S. Patent No. 8,650,513 Issued
2014-02-11 U.S. Patent No. 8,359,560 Issued
2015-08-21 U.S. Patent No. 9,792,394 Priority Date
2016-06-30 U.S. Patent No. 10,289,773 Priority Date
2016-09-15 Defendant’s alleged knowledge of ’513 Patent
2017-10-17 U.S. Patent No. 9,792,394 Issued
2018-01-01 Defendant’s alleged general knowledge of patents-in-suit (approximate)
2019-05-14 U.S. Patent No. 10,289,773 Issued
2020-02-07 Defendant’s alleged knowledge of ’394 Patent
2020-04-03 Defendant’s alleged knowledge of ’773 Patent
2025-03-21 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 8,607,173 - “Hierarchical Bottom-Up Clock Domain Crossing Verification”

  • Issued: December 10, 2013

The Invention Explained

  • Problem Addressed: The patent describes the process of verifying clock-domain crossings (CDC) in large, complex integrated circuits (ICs) as time-consuming and inefficient. Prior art approaches that required verification runs on an entire IC model were slow, while methods that partitioned the design often resulted in incomplete verification. (’173 Patent, col. 1:17-56; Compl. ¶27).
  • The Patented Solution: The invention proposes a hierarchical, bottom-up verification method. The process begins by performing CDC verification on a lower-level module of an IC design. Once verified, that module is replaced with a corresponding "abstraction module" that correctly identifies the clock-domain for its inputs and outputs. This process is repeated for progressively higher-level modules, using the abstraction models of the already-verified lower-level components. This approach is intended to streamline repeated verification cycles without the burden of full system-level runs. (’173 Patent, col. 1:63-2:9; Compl. ¶27). The concept is illustrated in the patent's Figure 1, which shows a nested hierarchy of modules M1 through M4. (Compl. ¶28; ’173 Patent, col. 3:36-57).
  • Technical Importance: This method aims to improve the speed and completeness of CDC verification, a critical step in designing large, modern System-on-a-Chip (SoC) devices. (Compl. ¶30).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶71).
  • The essential elements of claim 1 include:
    • identifying a module from among a plurality of modules that has not been previously abstracted or has not changed;
    • performing a CDC verification on the module in a bottom-up fashion by a computer processor device;
    • replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output;
    • repeating the identifying, performing, and replacing for each of the remaining modules; and
    • storing an updated model of the IC comprising at least a replaced module in storage.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 9,792,394 - “Accurate Glitch Detection”

  • Issued: October 17, 2017

The Invention Explained

  • Problem Addressed: The patent addresses inaccuracies in glitch detection for circuit designs. It explains that analyzing a lower-level abstraction (e.g., a "netlist") can identify many potential glitches, but typical tools may incorrectly flag a large number of them as problems ("false positives"). This is because such tools may not account for "glitch-blocking circuitry" which is more easily identified at a higher-level abstraction (e.g., "register-transfer level" or RTL). (’394 Patent, col. 6:8-15; Compl. ¶¶37, 43).
  • The Patented Solution: The invention describes a method that analyzes both higher-level and lower-level abstractions of a circuit design. First, the higher-level abstraction (e.g., RTL) is analyzed to identify glitch-blocking circuits, their corresponding "enable signals," and the "blocking values" that should cause the circuit to block glitches. Second, the lower-level abstraction (e.g., netlist) is analyzed to identify potential glitches. A design problem is detected if a potential glitch in the lower-level abstraction is not blocked when its corresponding enable signal is assigned the blocking value. (’394 Patent, col. 1:67-2:4; Compl. ¶38). Figure 3 of the patent illustrates this dual-abstraction analysis flow. (Compl. ¶41).
  • Technical Importance: This approach is intended to provide a more accurate and reliable glitch detection process by reducing false positives, which saves time and effort in debugging complex circuit designs. (Compl. ¶43).

Key Claims at a Glance

  • The complaint asserts independent claim 1. (Compl. ¶95).
  • The essential elements of claim 1 include:
    • analyzing a higher-level abstraction of the circuit design to identify (1) a set of glitch-blocking circuits, and (2) for each, an enable signal and a corresponding blocking value;
    • analyzing a lower-level abstraction of the circuit design to identify a possible glitch in a first signal;
    • identifying a first enable signal in the lower-level abstraction that corresponds to a glitch-blocking circuit; and
    • detecting a design problem in response to determining that the possible glitch is not blocked when the first enable signal is assigned a first blocking value.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 8,650,513 - “Reducing X-Pessimism in Gate-Level Simulation and Verification”

  • Issued: February 11, 2014. (Compl. ¶17).

Technology Synopsis

The patent addresses "X-pessimism," a phenomenon where conventional gate-level simulators propagate more indeterminate ("X") values than would occur in an actual silicon chip, particularly in circuits with reconvergent signal paths. The disclosed solution is a method that analyzes a design to identify blocks expected to exhibit X-pessimism and adds a "correcting block" to the design to produce the deterministic value the actual circuit would have produced. (Compl. ¶¶46-48).

Asserted Claims & Accused Features

  • Asserted Claims: Claim 1 is asserted. (Compl. ¶121).
  • Accused Features: The complaint accuses products including Ascent XV, Meridian RXV, and Verix SimFix, alleging they perform static analysis to identify "pessimism points" and use a correcting block to "fix X-pessimism." (Compl. ¶¶122, 125-126).

U.S. Patent No. 8,359,560 - “Hierarchical Bottom-Up Clock Domain Crossing Verification”

  • Issued: February 11, 2014. (Compl. ¶18).

Technology Synopsis

The patent addresses the difficulty of debugging complex IC designs across different levels of abstraction (e.g., RTL and gate-level). The invention enables synchronous debugging by linking two debugging processes or windows; when a user selects a signal in a first window corresponding to one design level, the corresponding signal in the second window for the other design level is automatically selected. (Compl. ¶¶52-53).

Asserted Claims & Accused Features

  • Asserted Claims: Claim 1 is asserted. (Compl. ¶141).
  • Accused Features: The complaint accuses products including iDebug, iVision, and SafeConnect, alleging they provide a multi-level debugging environment where signal checks are correlated between RTL and netlist levels and user selections in one view can update the display in another. (Compl. ¶¶142, 145, 148).

U.S. Patent No. 10,289,773 - “Reset Domain Crossing Management Using Unified Power Format”

  • Issued: May 14, 2019. (Compl. ¶19).

Technology Synopsis

The patent addresses inefficiencies that arise from handling Reset Domain Crossings (RDCs) and Power Domain Crossings (PDCs) with separate, often redundant, isolation circuits. The invention leverages information from the Unified Power Format (UPF) description, normally used for power management, to identify signals that create both an RDC and a PDC, thereby enabling the use of shared, optimized isolation structures. (Compl. ¶57).

Asserted Claims & Accused Features

  • Asserted Claims: Claim 1 is asserted. (Compl. ¶166).
  • Accused Features: The complaint accuses products including Meridian RDC and SafeConnect, alleging they utilize UPF descriptions to analyze "power related resets" during RDC verification, thereby identifying signals that are candidates for shared RDC/PDC isolation. (Compl. ¶¶167, 168, 170).

U.S. Patent No. 9,529,948 - “Minimizing Crossover Paths for Functional Verification of a Circuit Description”

  • Issued: December 10, 2013. (Compl. ¶20).

Technology Synopsis

The patent introduces a method to optimize functional verification by minimizing the number of "crossover paths" (signal paths crossing power domains) that require analysis. It leverages low-power information from power design description files (e.g., UPF) to identify which power state combinations are relevant, allowing for the generation of a reduced set of "functional crossover paths" for verification, thereby saving computational resources. (Compl. ¶¶63-65).

Asserted Claims & Accused Features

  • Asserted Claims: Claim 1 is asserted. (Compl. ¶187).
  • Accused Features: The complaint accuses products including Meridian CDC, Meridian RDC, and SafeConnect of performing functional verification by analyzing clock/reset structures while using power design descriptions (UPF format) to determine power state combinations and identify a reduced set of crossover paths for evaluation. (Compl. ¶¶188, 192, 196).

III. The Accused Instrumentality

Product Identification

  • The complaint names several accused software products across different infringement counts, including Meridian CDC, Meridian RDC, SafeConnect, Ascent XV, Verix SimFix, and iDebug. (Compl. ¶¶72, 96, 122, 142, 167, 188).

Functionality and Market Context

  • The accused products are software tools in the EDA market for static verification of IC designs. (Compl. ¶8). Their alleged functionalities correspond to the patented methods: Meridian CDC is alleged to perform hierarchical, bottom-up CDC verification using abstraction models stored in a "meta-database." (Compl. ¶¶74, 76). A diagram from a public presentation titled "Suggested Hierarchical CDC Flow" is provided to illustrate this process, showing how block-level analyses contribute to a "meta-database" used for top-level verification. (Compl. p. 28). The products are also alleged to provide a "Glitch Sign-off Flow" by analyzing both RTL and netlist abstractions to detect glitches. (Compl. ¶¶97-98, 105).

IV. Analysis of Infringement Allegations

U.S. Patent No. 8,607,173 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
identifying a module...that has not been previously abstracted or that has not changed since a previous abstraction, the module having an input and an output The Meridian CDC product is alleged to operate with a "hierarchical flow" that identifies an "IP or block" for verification. ¶74 col. 8:23-28
performing a CDC verification on the module in a bottom-up fashion by a computer processor device The accused Meridian CDC product is alleged to have a "bottom-up CDC verification capability." ¶75 col. 8:29-31
replacing the module with a corresponding abstraction module that correctly identifies a corresponding clock-domain for each of the input and the output... The Meridian CDC product allegedly creates and stores a "meta-database" which contains the abstraction modules for a verified component. ¶76 col. 8:32-37
repeating the identifying, performing, and replacing for each of the remaining modules from among the plurality of modules The accused products allegedly perform an iterative verification where CDC information from lower levels is saved and used at the top level for verification. ¶78 col. 8:38-41
storing an updated model of the IC comprising at least a replaced module in storage The Meridian CDC product allegedly creates and relies on a "transparent model database for hierarchical CDC analysis," which comprises the abstraction models. ¶79 col. 8:42-45

Identified Points of Contention

  • Scope Questions: The analysis may turn on whether the accused "meta-database" is coextensive with the claimed "abstraction module." A court may need to determine if the functional description of the "meta-database" in Defendant's materials meets the specific requirements of an "abstraction module" as defined in the patent.
  • Technical Questions: What evidence does the complaint provide that the Meridian CDC "bottom-up" flow performs the specific claimed sequence of identifying, performing, replacing, and repeating for each module in a hierarchical fashion, as opposed to a more general bottom-up analysis methodology?

U.S. Patent No. 9,792,394 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
analyzing a higher-level abstraction...to identify...a set of glitch-blocking circuits, and...an enable signal corresponding to the glitch-blocking circuit, and...a blocking value... The accused products allegedly verify logic at the "block level" (higher-level) and detect "synchronized CNTL signal(s) blocking or controlling DATA signals." ¶¶100, 102 col. 6:42-44
analyzing a lower-level abstraction of the circuit design to identify a possible glitch in a first signal... The accused products are alleged to perform "glitch" detection at the "Gate-Level Netlist" (lower-level). A presentation slide showing analysis of both "RTL" and "NETLIST" is provided as evidence. (Compl. p. 39). ¶¶100, 105 col. 6:44-50
identifying a first enable signal in the lower-level abstraction...that corresponds to a glitch-blocking circuit... The accused products allegedly identify corresponding circuitry between the higher-level (RTL) and lower-level (Netlist) abstractions to perform glitch detection. ¶106 col. 6:54-58
detecting a design problem...in response to determining that the possible glitch...is not blocked when the first enable signal is assigned a first blocking value... The accused products are used for "Glitch Sign-off," which the complaint alleges includes detecting design problems like "glitch propagation." ¶107 col. 6:63-7:2

Identified Points of Contention

  • Scope Questions: A central question may be whether analyzing "synchronized CNTL signal(s) blocking or controlling DATA signals" meets the specific claim requirements of identifying a "glitch-blocking circuit," an "enable signal," and a "blocking value." The definitional mapping between the accused functionality and these claim terms appears to be a potential point of dispute.
  • Technical Questions: Does the complaint's evidence of a "Glitch Sign-off" capability demonstrate the specific logical step required by the final claim element: determining that a glitch is not blocked precisely when its associated enable signal is assigned a blocking value?

V. Key Claim Terms for Construction

For the ’173 Patent

  • The Term: "abstraction module"
  • Context and Importance: This term is the core of the invention's hierarchical approach. The infringement theory depends on mapping the accused "meta-database" to this claim limitation. Practitioners may focus on this term because its construction will determine whether the accused product's method of storing and reusing block-level analysis results falls within the scope of the claims.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: Claim 1 itself defines the term functionally as a module "that correctly identifies a corresponding clock-domain for each of the input and the output." (’173 Patent, col. 8:34-36). This could support an interpretation covering any data structure that serves this purpose.
    • Evidence for a Narrower Interpretation: The detailed description explains that the abstraction includes specific types of information, such as "Sync(p)" (synchronizers reaching a port) and "Domain(p)" (the domain of flip-flops driving a port). (’173 Patent, col. 3:25-34). A defendant may argue that a true "abstraction module" must contain these specific categories of constraint data.

For the ’394 Patent

  • The Term: "glitch-blocking circuit"
  • Context and Importance: The invention's novelty rests on analyzing a higher level of abstraction specifically to identify these circuits. The infringement analysis requires that the accused products identify structures meeting this definition, rather than just general control logic.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests a broad functional scope, stating that "synchronization circuitry can also act as glitch-blocking circuitry." (’394 Patent, col. 4:7-8). Plaintiff may argue this supports construing the term to include any CDC synchronization circuit the accused tool identifies.
    • Evidence for a Narrower Interpretation: The patent's examples illustrate specific circuit structures intended to block glitches, such as the multiplexer-based circuit in Figure 2A. (’394 Patent, col. 5:12-28). A defendant may argue the term is limited to circuits having this explicit structural purpose, rather than any circuit that might incidentally block a glitch.

VI. Other Allegations

  • Indirect Infringement: For each asserted patent, the complaint alleges induced infringement, asserting that Defendant knew of the patents and intended for its customers to use the Accused Products in an infringing manner by providing user manuals, marketing materials, and technical support. (Compl. ¶¶87, 113). The complaint also advances a joint infringement theory for each asserted method claim, alleging Defendant directs and controls its customers' performance of the claimed steps through contractual agreements and active engagement via application engineers. (Compl. ¶¶82-86, 109-112).
  • Willful Infringement: The complaint alleges willful infringement for all six patents, based on alleged pre-suit knowledge. For the ’394, ’773, and ’513 patents, this knowledge is alleged to stem from specific citations made during the patent prosecution of Defendant’s own applications. (Compl. ¶21). For all patents, willfulness is also predicated on Defendant's alleged general review of Plaintiff’s patent portfolio around 2018 and its practice of benchmarking its products against Plaintiff's competing products. (Compl. ¶¶22, 88, 114).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of technical correspondence: does the functionality described in Defendant’s marketing and technical documents—such as creating a "meta-database" or analyzing "control signals"—perform the specific, multi-step processes required by the asserted claims, or is there a functional or definitional gap between the accused operations and the patented methods?
  • A key evidentiary question will be one of knowledge and intent: what is the legal and factual weight of patent citations that occurred during the prosecution of Defendant's own patent applications? The court may need to decide if these instances are sufficient to establish pre-suit knowledge and a high likelihood of willful infringement, or if Defendant can demonstrate a good-faith belief of non-infringement or invalidity that negates such claims.