DCT
1:25-cv-00504
MYW Semitech LLC v. Apple Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: MYW Semitech LLC (Delaware)
- Defendant: Apple Inc. (California)
- Plaintiff’s Counsel: Stamoulis & Weinblatt
- Case Identification: 1:25-cv-00504, D. Del., 07/07/2025
- Venue Allegations: Plaintiff alleges venue is proper in the District of Delaware because Apple Inc maintains a regular and established place of business in the district, has previously litigated in the forum without contesting venue, and has committed the alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s A-series and S-series processors, found in numerous Apple products, infringe three patents related to advanced semiconductor chip packaging technology.
- Technical Context: The technology at issue involves "fan-out" chip packaging, a method for creating smaller, more powerful, and more efficient integrated circuits by redistributing input/output connections on a carrier layer, which is critical for the performance and form factor of modern mobile devices.
- Key Procedural History: The three patents-in-suit are part of a direct continuation chain, sharing a common specification and priority claim. This relationship suggests that claim construction positions and invalidity arguments may overlap across the asserted patents.
Case Timeline
| Date | Event |
|---|---|
| 2012-09-26 | Earliest Patent Priority Date for '768, '763, and '306 Patents |
| 2016-09-16 | Launch of iPhone 7 with Accused A10 Chip (earliest accused product) |
| 2021-08-31 | U.S. Patent No. 11,107,768 Issues |
| 2022-12-27 | U.S. Patent No. 11,538,763 Issues |
| 2024-02-06 | U.S. Patent No. 11,894,306 Issues |
| 2025-07-07 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 11,107,768 - "Chip Package," issued August 31, 2021
The Invention Explained
- Problem Addressed: The patent’s background describes challenges in microelectronics as devices shrink. Increased miniaturization leads to higher resistance and parasitic capacitance in the metal interconnections, which degrades chip performance through voltage drops and signal delays. While flip-chip packaging offers improvements, it faces challenges with solder bump fatigue due to mismatches in the thermal coefficient of expansion (TCE) between the chip and the package. (U.S. Patent No. 11107768, col. 1:25-65).
- The Patented Solution: The invention proposes a chip package structure built upon a polymer layer. This layer contains vertical electrical pathways called "metal plugs" that pass through "through vias." An "interconnection scheme"—a network of patterned metal layers—is fabricated on top of this polymer layer to route signals between the metal plugs and a semiconductor chip positioned beneath the scheme. This architecture is designed to create a reliable, high-density connection platform for advanced semiconductor devices. (’768 Patent, col. 11:41-12:4; Abstract).
- Technical Importance: This type of structure relates to fan-out wafer-level packaging (FOWLP), a key technology that enables a higher number of input/output (I/O) connections in a smaller physical footprint, improving electrical performance and power efficiency for complex processors in compact devices. (Compl. ¶22).
Key Claims at a Glance
- The complaint asserts independent claim 1 and a number of dependent claims. (Compl. ¶27).
- The essential elements of independent claim 1 include:
- A first polymer layer with a specified thickness (100-300 micrometers) and coefficient of expansion (3-10 ppm/°C).
- A first metal plug containing copper vertically positioned in a first through via within the polymer layer.
- A second metal plug containing copper in a second through via, where the top surfaces of the first and second plugs are in the same horizontal plane.
- A first interconnection scheme built over the polymer layer's first surface, connecting to the metal plugs.
- A first metal bump positioned over the interconnection scheme.
- A first semiconductor chip positioned under the interconnection scheme. (Compl. ¶28).
- Plaintiff reserves the right to assert claims 2-5, 7-8, 10-11, 14-15, 16-17, 19-20, 22-23, and 25-28. (Compl. ¶27).
U.S. Patent No. 11,538,763 - "Chip Package," issued December 27, 2022
The Invention Explained
- Problem Addressed: As a continuation of the '768 patent, this patent addresses the same technical challenges of signal integrity and packaging reliability in miniaturized electronic devices. (’763 Patent, col. 1:21-53).
- The Patented Solution: The invention described is a chip package constructed using a "solid layer" made of a silicon and oxygen compound (such as glass). This layer is divided into at least two regions, with a plurality of copper plugs passing through vias in the "second region." An interconnection scheme is formed over this solid layer to connect the plugs to a semiconductor chip and external solder bumps, creating a substrate-less package. (’763 Patent, col. 7:15-24; Abstract).
- Technical Importance: This approach also pertains to FOWLP, providing an alternative material for the carrier/redistribution layer that offers specific dimensional and material properties beneficial for high-performance packaging. (Compl. ¶22).
Key Claims at a Glance
- The complaint asserts independent claim 1 and a number of dependent claims. (Compl. ¶45).
- The essential elements of independent claim 1 include:
- A solid layer comprising a compound of silicon and oxygen, with a specified thickness (100-300 micrometers) and defined first and second regions.
- A plurality of copper plugs in through vias located in the second region of the solid layer.
- A first interconnection scheme over the solid layer's first surface, connecting to the copper plugs.
- A first metal bump over the interconnection scheme.
- A first semiconductor chip under the interconnection scheme, which itself includes a third metal interconnect of a specified thickness (5-30 micrometers). (Compl. ¶46).
- Plaintiff reserves the right to assert claims 2-5, 7, 9-15, and 17. (Compl. ¶45).
U.S. Patent No. 11,894,306 - "Chip Package," issued February 6, 2024 (Compl. ¶18)
Technology Synopsis
This patent, part of the same family, also discloses a chip package structure addressing high-density interconnection needs. The claims describe a package using a solid layer (comprising silicon and oxygen) with through holes containing "copper posts" to facilitate connections between multiple semiconductor chips and various metal bumps in a compact, multi-chip configuration. (’306 Patent, col. 1:19-51).
Asserted Claims
Independent claim 10 and dependent claims 11-17 are asserted. (Compl. ¶61).
Accused Features
The accused features are the same Apple A-series and S-series chips, which allegedly embody the claimed package structure, including the solid layer with copper posts, interconnection schemes, and multiple semiconductor chips arranged relative to metal bumps. (Compl. ¶64-76).
III. The Accused Instrumentality
Product Identification
The complaint names a wide range of Apple consumer electronics, including various models of the iPhone, iPad, Apple Watch, Apple TV, HomePod, and Mac mini. (Compl. ¶21). The infringement allegations focus on the processors within these products, identified as the "Accused Chips": Apple A-series processors (A10 Fusion through A17 Pro) and Apple Watch S-series processors (S4 through S9). (Compl. ¶22).
Functionality and Market Context
The complaint alleges that the Accused Chips utilize "InFO PoP" (Integrated Fan-Out Package-on-Package) technology. (Compl. ¶22). This is a form of advanced packaging where a memory chip (DRAM) is stacked directly on top of a logic chip (SoC), enabling a thinner profile and improved electrical and thermal performance compared to traditional packaging methods. (Compl. ¶23). The complaint includes a diagram from a third-party source illustrating the InFO PoP structure, which features a high-density redistribution layer (RDL) to connect the logic and memory chips. (Compl. ¶23, p. 5). These processors serve as the central processing units for Apple's highest-volume and most profitable products, establishing their significant commercial importance.
IV. Analysis of Infringement Allegations
U.S. Patent No. 11,107,768 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a first polymer layer having a first surface and a second surface opposite to said first surface, wherein said first polymer layer has a thickness between 100 and 300 micrometers and has a coefficient of expansion between 3 and 10 ppm/° C. | The Accused Chips allegedly have a polymer layer with two opposing surfaces, a thickness between 100 and 300 micrometers, and the specified coefficient of expansion. A diagram labels this layer. | ¶31 | col. 17:10-18 |
| a first metal plug vertically in a first through via in said first polymer layer, wherein said first metal plug comprises a first copper layer | The Accused Chips allegedly have a metal plug positioned vertically in a through via within the polymer layer. This plug is alleged to contain copper. | ¶32-33 | col. 11:51-56 |
| a second metal plug vertically in a second through via in said first polymer layer ... wherein a top surface of said second metal plug and a top surface of said first metal plug are in the same horizontal plane | The Accused Chips allegedly have a second metal plug in a second through via, with its top surface being in the same horizontal plane as the first plug's top surface. | ¶34-35 | col. 11:57-63 |
| a first interconnection scheme over said first surface ... wherein said first metal interconnect is connected to said first metal plug | The Accused Chips allegedly have an interconnection scheme over the polymer layer made of metal interconnects, with the first interconnect connected to the first plug. | ¶36-37 | col. 12:1-4 |
| a first metal bump over said first interconnection scheme and said second metal plug, wherein said first metal bump comprises a tin-containing layer | The Accused Chips allegedly contain a metal bump over the interconnection scheme and metal plug, which comprises a tin-containing layer. | ¶38-39 | col. 14:26-34 |
| a first semiconductor chip under said first interconnection scheme | The Accused Chips allegedly contain a semiconductor chip under the interconnection scheme. A diagram identifies the "First semiconductor chip" as the "Logic" die. | ¶40 | col. 14:5-11 |
Identified Points of Contention
- Scope Questions: Claim 1 requires a "first polymer layer" having a specific coefficient of expansion (3-10 ppm/°C). A potential issue is whether the material used as the redistribution layer in Apple's InFO process qualifies as a "polymer layer" as that term is understood in the patent and whether it meets the claimed thermal property. The complaint asserts this limitation is met but does not provide supporting test data (Compl. ¶31).
- Technical Questions: The claim requires that the top surfaces of the first and second metal plugs be "in the same horizontal plane." The dispute may focus on the degree of planarity required by the claim language and whether the manufacturing process for the Accused Chips achieves that level of precision. The complaint's simplified diagram asserts this alignment but does not provide evidence of manufacturing tolerances (Compl. ¶35, p. 9).
U.S. Patent No. 11,538,763 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a solid layer having a first surface and a second surface opposite to said first surface ... wherein said solid layer comprises a compound of silicon and oxygen, wherein said solid layer has a thickness between 100 and 300 micrometers | The Accused Chips allegedly have a solid layer comprised of silicon and oxygen with the claimed thickness. A diagram labels this as the "Solid layer." | ¶49 | col. 7:15-24 |
| a plurality of copper plugs in a plurality of through vias in said second region of said solid layer | The Accused Chips allegedly have multiple copper plugs within through vias located in a "second region" of the solid layer. | ¶50-51 | col. 7:48-52 |
| wherein said first region has a width in a direction greater than a shortest distance between said sidewall of one of said plurality of through vias and said edge of said solid layer | The "first region" of the solid layer in the Accused Chips is alleged to have a width meeting the specific dimensional relationship relative to the through vias and the layer's edge. | ¶52 | col. 7:53-59 |
| a first interconnection scheme over said first surface ... wherein said first metal interconnect is connected to a first copper plug of said plurality of copper plugs | The Accused Chips allegedly have an interconnection scheme over the solid layer with metal interconnects connected to the copper plugs. | ¶53-54 | col. 8:1-12 |
| a first metal bump over said first interconnection scheme, wherein said first metal bump comprises a second metal layer and a tin-containing layer | The Accused Chips allegedly contain a metal bump over the interconnection scheme that includes a second metal layer and a tin-containing layer. | ¶55 | col. 8:13-17 |
| a first semiconductor chip under said first interconnection scheme, wherein said first semiconductor chip comprises a third metal interconnect on a first metal pad | The Accused Chips allegedly contain a semiconductor chip under the interconnection scheme, where the chip has a third metal interconnect on a metal pad. | ¶56-57 | col. 8:18-28 |
Identified Points of Contention
- Scope Questions: The interpretation of "solid layer... compris[ing] a compound of silicon and oxygen" will be critical. While this language may read on glass, a defendant could argue that the material used in its FOWLP process is a specialized dielectric or composite material that falls outside the claim's scope as understood from the patent's specification.
- Technical Questions: Claim 1 recites specific dimensional relationships for a "first region" relative to the placement of through vias and the edge of the solid layer. A factual dispute may arise as to how the "first region" and "second region" are defined and measured in the accused chips and whether they satisfy the claim's geometric constraints. The complaint asserts these limitations are met without providing measurements (Compl. ¶52).
V. Key Claim Terms for Construction
Term (from '768 Patent): "first polymer layer"
- Context and Importance: The identity and physical properties of this foundational layer are central to Claim 1 of the '768 Patent. The infringement analysis depends on whether the material used for the redistribution layer in the Accused Chips is properly characterized as a "polymer layer" that also meets the specific thickness and TCE requirements.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification discloses a variety of materials for the polymer layer, stating it may include "benzocyclobutane (BCB), polyimide (PI), polyurethane, epoxy resin, a parylene-based polymer, a solder-mask material, an elastomer, or a porous dielectric material." (’768 Patent, col. 17:21-27). This list may support a construction that is not limited to a single specific type of polymer.
- Evidence for a Narrower Interpretation: A defendant may argue that the term should be limited by the functional context and specific embodiments described, potentially arguing that the material in the accused device, while polymeric, functions differently or has a composition not contemplated by the patent.
Term (from '763 Patent): "solid layer compris[ing] a compound of silicon and oxygen"
- Context and Importance: This material limitation is a cornerstone of Claim 1 of the '763 Patent. Practitioners may focus on this term because the infringement theory hinges on the accused chips containing a layer meeting this precise chemical description.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes this layer as a "glass layer," a generally understood term. (’763 Patent, col. 7:15). This could support a broad definition encompassing various types of glass or glass-like materials.
- Evidence for a Narrower Interpretation: The specification explicitly lists examples, stating the material "may be included soda-lime glass, boro-silicate glass, alumo-silicate glass, fluoride glasses, phosphate glasses or chalcogen glasses." (’763 Patent, col. 7:18-22). A defendant might argue the claim scope is limited to the types of glass explicitly disclosed.
VI. Other Allegations
The complaint does not provide sufficient detail for analysis of indirect or willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of materials science and claim scope: do the materials used in Apple's InFO packaging process constitute a "polymer layer" with a specific coefficient of expansion as claimed in the ’768 patent, and a "solid layer compris[ing] a compound of silicon and oxygen" as claimed in the ’763 and ’306 patents? The outcome may depend on expert testimony regarding the precise composition and properties of the accused structures.
- A key evidentiary question will be one of structural correspondence: does the physical layout of the accused Apple chips—including the planarity of metal plugs, the definition of distinct "regions," and the specific thicknesses of various layers—map onto the precise structural and dimensional limitations recited in the asserted claims? The complaint's infringement theory relies on simplified diagrams, suggesting the defense may focus on purported mismatches revealed through detailed, cross-sectional analysis of the actual products.