DCT

1:25-cv-00629

Micron Technology Inc v. Netlist Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-00629, D. Del., 05/20/2025
  • Venue Allegations: Venue is asserted in Delaware based on Defendant Netlist, Inc. being a Delaware corporation and therefore subject to personal jurisdiction in the district.
  • Core Dispute: Plaintiff seeks a declaratory judgment that its High Bandwidth Memory (HBM) products do not infringe Defendant's patent related to stacked DRAM package architecture.
  • Technical Context: The dispute concerns architectural designs for high-density stacked dynamic random access memory (DRAM) packages, a key technology for increasing memory bandwidth and capacity in advanced computing systems.
  • Key Procedural History: This action follows a history of litigation between the parties. Defendant Netlist previously asserted two related patents ('060 and '160 patents) against Plaintiff Micron. The U.S. Patent and Trademark Office subsequently found all challenged claims of those patents unpatentable in inter partes review proceedings. The patent-in-suit ('087 patent) is a continuation from the same family. Netlist filed a complaint asserting the '087 patent against Micron in the Eastern District of Texas on May 19, 2025, one day before the patent was scheduled to issue. Micron filed this declaratory judgment action in Delaware on the day the '087 patent issued.

Case Timeline

Date Event
2010-11-03 '087 Patent Priority Date
2022-03-14 '087 Patent Application Filing Date
2022-06-10 Netlist files suit against Micron on related '060 and '160 patents (E.D. Tex.)
2023-04-12 IPR petitions filed against '060 and '160 patents
2024-02-10 E.D. Tex. litigation on '060 and '160 patents is stayed
2024-04-01 PTAB issues Final Written Decisions finding '060 and '160 patent claims unpatentable
2025-05-19 Netlist files suit against Micron on '087 patent (E.D. Tex.)
2025-05-20 U.S. Patent No. 12,308,087 Issues
2025-05-20 Micron files this Complaint for Declaratory Judgment (D. Del.)

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 12,308,087 - MEMORY PACKAGE HAVING STACKED ARRAY DIES AND REDUCED DRIVER LOAD

Issued: May 20, 2025

The Invention Explained

  • Problem Addressed: The patent addresses a challenge in designing memory packages with vertically stacked semiconductor dies (chips). As more dies are stacked to increase memory density, the electrical load on the driver circuit that sends signals to all the dies increases. This requires a larger, more power-hungry driver, which consumes valuable space and energy (’087 Patent, col. 2:25-34).
  • The Patented Solution: The invention proposes partitioning the signal paths to reduce the load on any single driver. Instead of one common interconnect (e.g., a signal line) serving all dies in the stack, the technology uses multiple, distinct interconnects. A first interconnect is dedicated to a first subset of dies, and a second interconnect is dedicated to a second subset of dies. This division of labor allows for the use of smaller, more efficient drivers for each partitioned group (’087 Patent, col. 4:5-15; Fig. 2). The patent describes this partitioning for both command/address signals and data signals, using through-silicon vias (TSVs) to create the vertical connections through the stacked dies (’087 Patent, col. 5:29-46, col. 7:14-24).
  • Technical Importance: This load-reduction architecture is intended to enable the creation of higher-density, multi-die memory packages, such as High Bandwidth Memory (HBM), without the prohibitive power and area costs associated with driving a high-capacitance, unified bus (’087 Patent, col. 4:1-4).

Key Claims at a Glance

  • The complaint states the ’087 Patent has six independent claims (1, 2, 12, 20, 21, and 22) and centers its non-infringement argument on claim 1 (Compl. ¶27, ¶29).
  • The essential elements of independent claim 1 include:
    • A DRAM package with stacked DRAM dies comprising a "first plurality" and a "second plurality" of dies.
    • Terminals for receiving command/address (C/A) and data signals.
    • Die interconnects, including first and second C/A interconnects and first and second data interconnects, which use through-silicon vias (TSVs).
    • A control die with conduits coupled to the die interconnects.
    • A limitation requiring the first C/A interconnect to be in electrical communication only with the first plurality of DRAM dies and not the second.
    • A corresponding limitation requiring the second C/A interconnect to be in electrical communication only with the second plurality of DRAM dies and not the first.
    • Similar partitioning limitations for the first and second data interconnects.
    • A limitation requiring control logic to operate in response to C/A signals that "do not include any chip select signal."
    • Further limitations detailing separate unidirectional interconnects for read and write signal paths.

III. The Accused Instrumentality

Product Identification

  • Micron's HBM3E, HBM4, and HBM4E products (Compl. ¶23).

Functionality and Market Context

  • The complaint identifies the accused instrumentalities as High Bandwidth Memory (HBM) products that are compliant with JEDEC memory standards (Compl. ¶13, ¶16). It does not, however, provide specific technical details regarding the internal architecture, interconnect topology, or operational modes of these products. The core allegations are directed at a mismatch with the patent's claimed architecture rather than a detailed analysis of the products' functions.

IV. Analysis of Infringement Allegations

The complaint alleges non-infringement and does not provide a detailed mapping of the accused products' features to the claim elements. Instead, it presents a narrative theory of non-infringement.

The complaint asserts that Micron’s products do not infringe because they "do not employ, incorporate, or otherwise make use of, all of the limitations of the claim" (Compl. ¶28). The central theory of non-infringement focuses on the patent's strict architectural partitioning requirements. For claim 1, the complaint specifically alleges that Micron's HBM products do not satisfy the limitations that require a "first C/A interconnect" to be in electrical communication exclusively with a "first plurality of DRAM dies" and a "second C/A interconnect" to be exclusively in communication with a "second plurality of DRAM dies" (Compl. ¶29). The complaint makes a parallel argument for the data interconnects. No probative visual evidence provided in complaint.

  • Identified Points of Contention:
    • Technical Question: The primary point of contention is factual and technical: What is the actual electrical interconnect architecture within Micron's HBM3E, HBM4, and HBM4E products? The complaint puts at issue whether these products implement the partitioned bus structure recited in the claims, where specific interconnects are electrically isolated and dedicated to distinct, non-overlapping groups of DRAM dies.
    • Evidentiary Question: What evidence will discovery yield regarding the internal design of Micron's HBM products? The complaint's conclusory allegation of non-infringement frames this as the central dispute to be resolved through discovery and expert analysis.

V. Key Claim Terms for Construction

  • The Term: "first plurality of DRAM dies" and "second plurality of DRAM dies"

    • Context and Importance: The invention's core concept of load-partitioning is defined by separating the stack into at least two distinct "pluralities." How these groups are defined—whether by physical position, logical function, or electrical connectivity—is fundamental to the infringement analysis. Practitioners may focus on this term because if Micron's HBM architecture does not group dies into such distinct, non-overlapping sets, it may not meet this foundational limitation.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: A party could argue that "plurality" simply means a group of two or more, and that the patent does not restrict how these pluralities are formed. The specification refers to them as "subsets," which could imply flexibility in grouping (’087 Patent, col. 16:40-55).
      • Evidence for a Narrower Interpretation: The figures and associated description show the pluralities as distinct, physically separate groups of dies within the stack (e.g., a lower group and an upper group) (’087 Patent, Fig. 2; col. 5:47-56). A party could argue this context requires the pluralities to be discrete and non-overlapping.

  • The Term: "not in electrical communication with"

    • Context and Importance: This negative limitation is the crux of the claimed isolation. Micron’s non-infringement theory relies on its products failing to meet this requirement (Compl. ¶29). The key question will be the degree of isolation required.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation (of the term, resulting in narrower claim scope): A party defending the patent may argue that this phrase means the absence of a functional, intended signal path. The specification describes signals passing through vias on a die without being electrically connected to that die's circuitry, supporting a distinction between physical proximity and functional "communication" (’087 Patent, col. 7:25-40).
      • Evidence for a Narrower Interpretation (of the term, resulting in broader claim scope): An accused infringer could argue that the plain meaning of "electrical communication" is broad and that any significant signal coupling, such as parasitic capacitance or crosstalk between allegedly separate interconnects, would violate this negative limitation.

  • The Term: "a second conduit of the second data conduits is coupled between the second data interconnect and the first data terminal" (Claim 1(i))

    • Context and Importance: This language is highly unusual. Claim 1, element (i), recites that the conduit for the first data interconnect and the conduit for the second data interconnect are both coupled to the same "first data terminal" (Compl. ¶27). Practitioners may focus on this term because it appears to create an electrical bottleneck, seemingly contradicting the patent's stated goal of load reduction through partitioning.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation (e.g., a correctable error): A party could argue this is an obvious scrivener's error that should be read as "second data terminal" to align with the patent's overall disclosed purpose. The specification repeatedly emphasizes separating signal paths to reduce load (’087 Patent, col. 2:25-34, col. 4:1-4).
      • Evidence for a Narrower Interpretation (i.e., a literal reading): An accused infringer will likely argue that claim language is unambiguous and must be enforced as written. While not explicitly shown in the figures, this configuration could represent a specific embodiment (e.g., using time-division multiplexing at the terminal) that is captured by the claim language, presenting a strong basis for a non-infringement argument if the accused device does not funnel separate paths back to a single terminal.

VI. Other Allegations

  • Indirect Infringement: The complaint seeks a declaration of non-infringement for both direct and indirect infringement but provides no specific factual allegations to rebut a theory of indirect infringement (Compl. ¶32).
  • Willful Infringement: Willfulness is not alleged, as this is a declaratory judgment action of non-infringement filed by the accused infringer.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be factual and evidentiary: does the internal architecture of Micron's HBM products feature the strictly partitioned command, address, and data interconnects required by claim 1? The outcome will depend heavily on technical evidence revealed during discovery.
  • A second critical issue will be one of claim construction, particularly the scope of the negative limitation "not in electrical communication with." The court's definition—whether it requires absolute electrical isolation or merely the absence of a functional signal path—will significantly impact the infringement analysis.
  • Finally, the case may turn on the interpretation of potentially contradictory claim language in claim 1(i), which appears to route two separate data paths back to a single terminal. Whether this is read literally, providing a clear non-infringement path, or is interpreted as a correctable error in light of the specification, will be a key legal question for the court.