Empire Technology Development LLC v. Advanced Micro Devices Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Empire Technology Development LLC (Delaware)
  • Defendant: Advanced Micro Devices, Inc. (Delaware)
  • Plaintiff’s Counsel: Potter Anderson & Corroon LLP
• Case Identification: 1:25-cv-01049, D. Del., 08/21/2025
• Venue Allegations: Venue is alleged to be proper in the District of Delaware because AMD is a Delaware corporation and therefore a resident of the district.
• Core Dispute: Plaintiff alleges that Defendant’s multicore processors, including its Ryzen and EPYC product lines, infringe patents related to efficient on-chip communication and leakage current-based power management.
• Technical Context: The technologies at issue concern fundamental challenges in modern semiconductor design: optimizing data routing between processor cores and managing power consumption to improve performance and efficiency.
• Key Procedural History: The complaint notes that application publications for both patents-in-suit were cited during the prosecution of patent applications filed by Intel Corporation, a major competitor in the microprocessor field, which may suggest the patents' perceived relevance within the industry.

Case Timeline

Date	Event
2014-07-07	’850 Patent Priority Date
2014-08-25	’370 Patent Priority Date
2016-06-14	U.S. Patent No. 9,367,370 Issued
2017-06-06	U.S. Patent No. 9,671,850 Issued
2020-11-05	Alleged first infringement of ’370 Patent (AMD Ryzen with Zen 3 launch)
2021-03-15	AMD EPYC processors with Zen 3 microarchitecture released
2022-04-01	Alleged first infringement of ’850 Patent (AMD products with Zen 3+ launch)
2025-08-21	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 9,367,370 - “NOC LOOPBACK ROUTING TABLES TO REDUCE I/O LOADING AND OFF-CHIP DELAYS” (Issued June 14, 2016)

The Invention Explained

• Problem Addressed: The patent addresses inefficiencies in multicore processors where messages between different processes running on cores within the same physical chip are routed through an external, "off-chip" network. This process is described as introducing "undesirable and unnecessary network delays and input/output loading at the hardware" (’370 Patent, col. 3:26-33).
• The Patented Solution: The invention proposes a "loopback simulator" operating at the processor's hardware layer that intercepts outgoing messages (’370 Patent, col. 4:44-55). Using a "core-address-to-IP-address map," the system determines if a message's destination is another core on the same chip. If so, the simulator redirects the message directly to the destination core via on-chip communication, avoiding the latency of the off-chip network (’370 Patent, col. 4:56-62; Abstract).
• Technical Importance: This technology aimed to increase the performance of multicore processors, particularly in datacenter and cloud computing environments where communication between virtual machines or processes on a single server is common (’370 Patent, col. 1:10-19).

Key Claims at a Glance

• The complaint asserts independent claim 14 (Compl. ¶23).
• Essential elements of claim 14 include:
  • A multicore processor with a plurality of processor cores.
  • A controller configured to identify processes on the cores that are adapted to communicate via an off-chip network.
  • The controller is further configured to generate a "core-process-to-IP-address map" and use it to identify a destination core and associated data for a message.
  • A "loopback simulator at a processor hardware layer" that delivers messages between processes using on-chip communication by processing the identified data back into "on-chip flits" for delivery to the destination core.
• The complaint does not explicitly reserve the right to assert dependent claims but states its examples are non-limiting (Compl. ¶32).

U.S. Patent No. 9,671,850 - “LEAKAGE CURRENT VARIABILITY BASED POWER MANAGEMENT” (Issued June 6, 2017)

The Invention Explained

• Problem Addressed: As semiconductor manufacturing processes shrink transistor sizes, "leakage current" (power that leaks from transistors when they are inactive) becomes a more significant source of power consumption (’850 Patent, col. 1:16-24). The patent also notes that this leakage can vary dramatically between different functional sub-units on the same chip due to manufacturing variations, making one-size-fits-all power management ineffective (’850 Patent, col. 1:24-29).
• The Patented Solution: The invention describes a method for dynamic and granular power management. It involves receiving "computation data from a power controller and one or more processor instruction counters" and using this data to generate a "micro-architectural leakage map" of a processor core (’850 Patent, Abstract). This map, which quantifies leakage for different sub-units, is then used to make intelligent power-saving decisions, such as deactivating a leaky sub-unit and migrating its workload (a "thread") to a more efficient one (’850 Patent, col. 6:8-23).
• Technical Importance: The technology provides a method for adapting to inherent manufacturing variability at the micro-architectural level, enabling more effective power management and improving the overall efficiency of advanced processors (’850 Patent, col. 1:4-9).

Key Claims at a Glance

• The complaint asserts independent claim 12 (Compl. ¶66).
• Essential elements of claim 12 include:
  • A method involving a memory and a processor executing a power management application.
  • Receiving computation data from a power controller and processor instruction counters (PICs).
  • Generating a table of "linear combination samples" from the data, which includes a power usage value for sub-units of a core.
  • Generating a "micro-architectural leakage map" from the table.
  • A multi-step process of responding to the map by directing threads between sub-units, deactivating and reactivating sub-units, and migrating threads between them.
• The complaint does not explicitly reserve the right to assert dependent claims but states its examples are non-limiting (Compl. ¶74).

III. The Accused Instrumentality

Product Identification

The accused products are AMD multicore processors, specifically the Ryzen and EPYC series, that incorporate the "Zen 3" microarchitecture or later for the ’370 Patent, and the "Zen 3+" microarchitecture or later for the ’850 Patent (Compl. ¶¶27, 69).

Functionality and Market Context

• The complaint alleges that AMD's Zen 3 microarchitecture fundamentally changed inter-core communication by implementing a "Core Complex" (CCX) in which eight cores share a single, large L3 cache. This is contrasted with the prior Zen 2 architecture, where communication between cores in different complexes on the same die allegedly had to be routed off-chip (Compl. ¶54). This shared L3 cache is alleged to provide fast, on-chip communication that constitutes the claimed "on-chip loopback" (Compl. ¶¶57-58). A diagram comparing the Zen 2 and Zen 3 layouts illustrates the architectural shift to a unified L3 cache shared by eight cores (Compl. p. 19).
• For the ’850 Patent, the complaint points to AMD's marketing and technical documents describing "adaptive power management features" in the Zen 3+ and newer architectures (Compl. ¶76). These features are described as a "5 layers of power optimization" approach that includes optimizations at the "core architecture," "SoC architecture," and "system software" levels (Compl. ¶78). An AMD slide details this five-layer approach (Compl. p. 28). The complaint alleges these features are specifically "optimized for better leakage" and are designed to take advantage of "inherent variabilities between parts," thereby practicing the claimed power management method (Compl. ¶¶79, 82).

IV. Analysis of Infringement Allegations

’370 Patent Infringement Allegations

Claim Element (from Independent Claim 14)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
[a] a plurality of processor cores	AMD's EPYC and Ryzen processors contain multiple cores, with some models containing up to 192 cores.	¶¶34-36	col. 4:10-12
[b] a controller configured to identify one or more processes... adapted to communicate with each other via an off-chip network	The AMD I/O Die (IOD) contains controllers (e.g., Unified Memory Controllers) and uses Infinity Fabric technology to connect multiple Core Complex Dies (CCDs) to each other and to external memory and I/O, constituting an off-chip network.	¶¶42-43, 47	col. 2:37-43
[c] generate a core-process-to-IP-address map	The controllers within the IOD are alleged to be configured to generate such a map.	¶50	col. 4:42-43
[d] identify a designation processor core for a message based on the... map	The controllers are alleged to be configured to identify a destination core for a message based on the map.	¶50	col. 16:51-54
[e] identify data associated with a message to be delivered	The controllers are alleged to be configured to identify data for delivery to the destination core.	¶50	col. 16:55-57
[f] a loopback simulator at a processor hardware layer... configured to deliver messages... via on-chip communication by processing the identified data back into one or more on-chip flits	The redesigned Zen 3 Core Complex (CCX), where eight cores share a common L3 cache, is alleged to be the loopback simulator. This shared cache enables low-latency, on-chip communication between cores within the CCX.	¶¶54, 57-58	col. 4:44-55

• Identified Points of Contention:
  • Scope Questions: A central question will be whether an architectural feature like a shared L3 cache, which provides a passive communication path, meets the claim limitation of a "loopback simulator." The term "simulator" may suggest an active component that mimics the behavior of an off-chip network, rather than a direct hardware connection.
  • Technical Questions: The complaint asserts in a conclusory manner that the accused controllers perform the functions of generating a map and identifying destination cores based on it (elements [c]-[e]). A point of contention will be what evidence demonstrates that the accused products actually generate a "core-process-to-IP-address map" as required by the claim.

’850 Patent Infringement Allegations

Claim Element (from Independent Claim 12)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
[c] receive computation data from a power controller and one or more processor instruction counters (PIC)	AMD's System Management Unit (SMU) is alleged to manage power by integrating "telemetry" from agents on each die, including data on power, performance, and core idle states. AMD's CPPC capability is alleged to communicate "per-thread utilization to the OS."	¶¶88, 90, 93	col. 10:39-43
[d] generate a table of linear combination samples... wherein each... include a power usage value for a sub-unit of the selected core	AMD's power management framework is alleged to take advantage of "inherent variabilities between parts," which suggests sub-unit-specific data is used.	¶82	col. 5:16-20
[e] generate a micro-architectural leakage map of the selected core from the linear combination samples	AMD's marketing materials state that its Zen 3+ core architecture is "optimized for better leakage." An AMD slide explicitly lists "LEAKAGE" as a feature for which "all design elements [are] optimized" (Compl. p. 29).	¶79	col. 5:45-50
[f-i] direct a thread... reactivate the second sub-unit; execute a thread migration operation... move the thread back	AMD's Zen 3+ architecture is alleged to feature an "enhanced CC1 state" to "trigger sleep if a core isn't being utilized," "deep SoC power partitioning," and the ability to reassign threads.	¶¶95-96, 98	col. 6:8-23

• Identified Points of Contention:
  • Scope Questions: Does AMD's high-level "power management framework" constitute the specific, multi-step method claimed? The infringement theory appears to map general marketing statements (e.g., "optimized for better leakage") onto specific claim limitations (e.g., "generate a micro-architectural leakage map").
  • Technical Questions: The complaint does not provide direct evidence of how AMD's processors implement their power management. Key questions will be whether AMD's system actually generates a data structure equivalent to a "table of linear combination samples" or a "micro-architectural leakage map," and whether it performs the highly specific sequence of thread migration, deactivation, and reactivation recited in elements [f] through [i].

V. Key Claim Terms for Construction

For the ’370 Patent

• The Term: "loopback simulator at a processor hardware layer"
• Context and Importance: This term is the central feature of the invention. The dispute will likely focus on whether this term can read on a passive architectural design, like a shared cache, or if it requires a distinct, active component that simulates network behavior.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The patent's stated goal is to reduce off-chip delays by redirecting messages on-chip (’370 Patent, col. 3:30-34). Language describing the function—"to deliver messages between the process(es) via on-chip communication"—could support construing the term to cover any hardware structure that achieves this end result (col. 2:41-43).
  • Evidence for a Narrower Interpretation: The specification explicitly depicts a "loopback controller" that contains a "loopback simulator," suggesting a specific functional block rather than a general-purpose cache (’370 Patent, Fig. 3, col. 4:40-44). The word "simulator" itself implies mimicking the behavior of something else (the off-chip network), which may require more than just providing a direct communication path.

For the ’850 Patent

• The Term: "generate a micro-architectural leakage map"
• Context and Importance: This is the foundational step of the claimed power management method. The viability of the infringement case depends on whether AMD's power management techniques, which consider leakage, can be characterized as "generating" such a "map."
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Practitioners may argue that any system that gathers and algorithmically uses sub-unit-specific power data to make management decisions is implicitly generating a functional equivalent of a "map," even if it is not stored as a formal data table.
  • Evidence for a Narrower Interpretation: The claim requires the map to be generated "from the linear combination samples within the table" (’850 Patent, col. 15:45-48). The specification describes a specific mathematical process of using instruction counters and power data to solve for leakage values (’850 Patent, col. 5:1-14). This suggests that a specific data generation and processing method is required, not just a general awareness of leakage.

VI. Other Allegations

• Indirect Infringement: The complaint alleges both induced and contributory infringement for both patents. Inducement is based on AMD allegedly providing customers and end-users with products along with "instructions, documentation, white papers, product manuals, datasheets, marketing, and advertisements" that instruct on their use (Compl. ¶¶29, 71).
• Willful Infringement: Willfulness is alleged for both patents, based on AMD’s knowledge of the patents and the alleged infringement "at least since receiving notice of this Complaint" (Compl. ¶¶60, 100).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: Can the term "loopback simulator," which the patent describes as an active controller that mimics network behavior, be construed to cover the accused architectural feature of a "shared L3 cache" that provides a passive, direct communication path between cores?
• A key evidentiary question will be one of technical implementation: Does the complaint provide sufficient evidence that AMD's power management systems perform the specific, multi-step method of Claim 12 of the ’850 Patent—particularly the generation of a "micro-architectural leakage map" from "linear combination samples"—or do AMD's features represent general optimizations that do not map to the claimed process?
• The case will likely focus on whether the asserted claims cover high-level functionality (on-chip communication, leakage-aware power management) or require the specific implementations detailed in the patents, which the complaint alleges are met through the operation of architectural features and marketing descriptions rather than direct evidence of the claimed processes.