DCT

1:25-cv-01465

VeriFone Inc v. Near Field Electronics LLC

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:25-cv-01465, D. Del., 12/03/2025
  • Venue Allegations: Venue is based on Defendant NFE's alleged residence in the District of Delaware, citing a registered address in Wilmington.
  • Core Dispute: Plaintiff Verifone seeks a declaratory judgment that its point-of-sale payment terminals do not infringe five patents owned by Defendant NFE, and that the patents are invalid, in response to lawsuits NFE filed against Verifone's customers.
  • Technical Context: The patents relate to semiconductor-level technologies for managing communication protocols, interface configurations, power consumption, and signal detection in electronic devices.
  • Key Procedural History: This declaratory judgment action follows at least ten lawsuits filed by NFE in the Eastern District of Texas against Verifone’s customers. The complaint states NFE has threatened to file over two hundred additional lawsuits. The parties previously engaged in discussions where Verifone provided NFE with technical non-infringement arguments and invalidating prior art, which did not resolve the dispute.

Case Timeline

Date Event
2000-06-21 ’201 Patent Priority Date
2000-07-25 ’071 Patent Priority Date
2000-08-28 ’727 Patent Priority Date
2002-06-28 ’350 Patent Priority Date
2004-02-10 ’201 Patent Issue Date
2004-05-25 ’071 Patent Issue Date
2005-01-11 ’531 Patent Priority Date
2005-10-25 ’350 Patent Issue Date
2006-02-07 ’727 Patent Issue Date
2008-05-13 ’531 Patent Issue Date
2021-11-28 ’071 Patent Expiration Date (Alleged)
2022-01-31 ’201 Patent Expiration Date (Alleged)
2022-04-14 ’727 Patent Expiration Date (Alleged)
2022-09-18 ’350 Patent Expiration Date (Alleged)
2025-12-03 Complaint Filing Date
2026-03-19 ’531 Patent Expiration Date (Alleged)

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,691,201 - "Dual Mode USB-PS/2 Device"

The Invention Explained

  • Problem Addressed: The patent describes the challenge for manufacturers of peripheral devices (like computer mice) that need to support multiple communication protocols, such as USB and PS/2, to ensure broad compatibility. Conventional approaches required separate sets of external components for each protocol, increasing cost, circuit board size, and firmware complexity (’201 Patent, col. 1:25-49).
  • The Patented Solution: The invention proposes a single integrated circuit that automatically detects the signaling protocol of a connected bus (e.g., USB or PS/2) and configures itself to operate in the correct mode. This is accomplished using a shared set of input/output pins, eliminating the need for redundant external hardware (’201 Patent, Abstract; col. 2:51-61).
  • Technical Importance: This integrated solution aimed to simplify peripheral design, reduce manufacturing costs, and conserve space on the device's printed circuit board (’201 Patent, col. 2:4-10).

Key Claims at a Glance

  • The complaint asserts non-infringement of claims including independent claims 13 (apparatus) and 14 (method) (Compl. ¶41, ¶45, ¶49).
  • Independent Claim 14 (Method):
    • (A) detecting a signaling protocol of a bus connected to an integrated circuit that operates in a plurality of signaling protocols; and
    • (B) configuring said integrated circuit to communicate in one of said plurality of signaling protocols in response to said detected signaling protocol of said connected bus, wherein each of said selected protocols operate over said connected bus through a single set of pins.

U.S. Patent No. 6,742,071 - "Real-Time I/O Processor Used To Implement Bus Interface Protocols"

The Invention Explained

  • Problem Addressed: The patent addresses the limitations of conventional bus interface designs, which were either specific to a single protocol (lacking flexibility) or were user-programmable but relied on fixed, pre-set "wait-states," making them inefficient for implementing complex or high-speed signaling protocols (’071 Patent, col. 1:14-48).
  • The Patented Solution: The invention discloses a real-time input/output (I/O) processor that functions as a generic, programmable interface. The processor uses a state machine architecture, driven by instructions from a memory or lookup table, to generate and respond to control signals on a clock-cycle basis. This allows it to dynamically implement the precise timing and logic of various bus protocols (’071 Patent, Abstract; col. 2:51-54).
  • Technical Importance: This architecture provides a flexible, processor-based solution that allows a single chip design to be adapted to multiple existing and future bus standards, reducing design risk for hardware manufacturers (’071 Patent, col. 2:54-60).

Key Claims at a Glance

  • The complaint asserts non-infringement of claims including independent claims 9 (circuit) and 15 (method) (Compl. ¶58, ¶62, ¶66).
  • Independent Claim 15 (Method):
    • (A) generating a plurality of first control signals in response to a current state of a processor;
    • (B) progressing to a next state based on said current state, at least one internal control signal of said first control signals and an input signal received from said external bus;
    • (C) driving at least one output control signal of said first controls signals onto said external bus; and
    • (D) updating said current state to said next state.

U.S. Patent No. 6,959,350 - "Configurable USB Interface With Virtual Register Architecture"

  • Technology Synopsis: The patent addresses the problem of hard-coded endpoint configurations in USB interface controllers, which limits flexibility (Compl. ¶20; ’350 Patent, col. 1:19-28). The proposed solution is an interface controller that uses a Hardware Description Language (HDL)-based "configuration package" to generate configuration circuitry, allowing the controller to be adapted for different endpoint structures without fabricating new hardware (’350 Patent, Abstract).
  • Asserted Claims: The complaint seeks a declaratory judgment of non-infringement of at least claim 10 (Compl. ¶75).
  • Accused Features: The complaint alleges that NFE’s infringement theory targets the NXP PN512 component within the Accused Products, specifically how its interface is configured via logic levels applied to its control pins (Compl. ¶80).

U.S. Patent No. 6,996,727 - "Power Supply For Universal Serial Bus Interface With Programmable Bus Pullup Resistor"

  • Technology Synopsis: The patent describes a power supply device for a USB interface designed to reduce power consumption (Compl. ¶21). The solution involves a device that can switch between a standard voltage level and a "power down" voltage level, using a programmable resistor controlled by a register loaded from nonvolatile memory to manage current flow in different modes (’727 Patent, Abstract).
  • Asserted Claims: The complaint seeks a declaratory judgment of non-infringement of at least claim 18 (Compl. ¶92).
  • Accused Features: The complaint alleges that NFE’s infringement theory targets the NXP PN512 component, focusing on its ability to regulate current consumption based on voltage levels at its transmitter pins (TX1 and TX2) (Compl. ¶97).

U.S. Patent No. 7,373,531 - "Signal Detection Method, Frequency Detection Method, Power Consumption Control Method..."

  • Technology Synopsis: The patent addresses wasteful power consumption in electronic devices when no input signal is being processed (Compl. ¶22; ’531 Patent, col. 1:36-42). The invention is a method for detecting the presence of an active signal by monitoring the "through current" that flows in series-connected transistors only when the input signal is changing state. When this through current ceases, a power-saving signal is generated (’531 Patent, Abstract).
  • Asserted Claims: The complaint seeks a declaratory judgment of non-infringement of at least claim 2 (Compl. ¶112).
  • Accused Features: The complaint alleges that NFE’s infringement theory targets the NXP PN512 component’s RF level detector, which NFE claims detects a "through current caused by modulations in an RF field" (Compl. ¶117). The complaint includes an excerpt from an NFE claim chart showing a block diagram of the PN512 to illustrate this theory (Compl. p. 47).

III. The Accused Instrumentality

Product Identification

Verifone’s M400, MX915, and MX925 point-of-sale payment terminals (the "Accused Products") (Compl. ¶3, ¶28). The complaint provides images of the three accused payment terminal models (Compl. p. 2).

Functionality and Market Context

The Accused Products are described as world-class point-of-sale electronic payment devices used by merchants globally (Compl. ¶3). The complaint asserts that NFE's infringement allegations are not directed at the terminals as a whole, but at a specific internal component: the "NXP PN512 Front-End" integrated circuit, which is equipped in the devices (Compl. ¶13). Verifone’s non-infringement arguments for all five asserted patents are based on the specific technical operation of this PN512 component (Compl. ¶46, ¶63, ¶80, ¶97, ¶117).

IV. Analysis of Infringement Allegations

The complaint references claim-chart exhibits from other lawsuits that are not provided. The narrative infringement theories, as characterized by Verifone, are summarized below in prose.

’201 Patent Non-Infringement Allegations

Verifone alleges that NFE's infringement theory fails because the accused NXP PN512 component does not perform the central steps of claim 14 (Compl. ¶50, ¶51). Specifically, Verifone contends that the PN512 chip does not "detect[] a signaling protocol" because its communication protocol is fixed and is never detected from a bus (Compl. ¶50). Furthermore, Verifone argues that the PN512 does not operate in a "plurality of signaling protocols" as required by the claim, but rather communicates internally using only a single protocol (Compl. ¶51). This frames a potential dispute over whether the PN512's method of operation meets the claim requirements of active detection and multi-protocol capability.

’071 Patent Non-Infringement Allegations

Verifone’s non-infringement argument centers on limitation 15[c], which requires "driving at least one output control signal... onto said external bus" (Compl. ¶67). The complaint states that NFE alleges this element is met by the PN512 propagating an interrupt request to an IRQ pin (Compl. ¶67). Verifone counters this on two grounds. First, it argues that NFE fails to show that this single IRQ pin is connected to an "external bus," which Verifone implies is a broader structure than a single pin (Compl. ¶68). Second, Verifone contends that the interrupt requests are triggered by a timer or an alert, which does not satisfy other claim limitations requiring the signal generation to be responsive to the processor's "current state" (Compl. ¶67).

V. Key Claim Terms for Construction

Term: "detecting a signaling protocol" (’201 Patent, claim 14)

  • Context and Importance: The definition of this term is critical, as Verifone’s core non-infringement argument is that the accused PN512 chip does not "detect" a protocol but is instead configured to use a single, predetermined protocol (Compl. ¶50). Practitioners may focus on this term because the dispute appears to center on whether setting an operational mode via static logic levels on pins qualifies as "detecting a signaling protocol of a connected bus."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent emphasizes a device that can "automatically select" a protocol "without user input" ('201 Patent, col. 2:51-54). A party might argue that "detecting" should be construed broadly to encompass any automated means of determining the appropriate protocol, including sensing the state of configuration pins upon connection.
    • Evidence for a Narrower Interpretation: The claim language specifies detecting the protocol "of a connected bus" ('201 Patent, col. 7:1-3). A party could argue this requires an active analysis of signals transmitted over the bus itself, rather than reading a static internal configuration.

Term: "external bus" (’071 Patent, claim 15)

  • Context and Importance: Verifone's non-infringement argument for the ’071 patent hinges on its contention that NFE improperly equates a single "IRQ pin" with an "external bus" (Compl. ¶68). The viability of NFE's infringement theory may depend on whether a single signal line can meet the definition of a "bus."
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent does not appear to provide an explicit definition of "external bus." A party could argue that in the context of interfacing with external logic, any external conductive path used for signaling, even a single line, could be considered a "bus."
    • Evidence for a Narrower Interpretation: The background section discusses interfacing with standard protocols like EPP, ATAPI, and ISA, which are conventionally understood to be multi-line buses (’071 Patent, col. 1:20-25). A party might argue that "external bus" should be construed in this context to mean a multi-conductor pathway for parallel data or control signals, not a single interrupt line.

VI. Other Allegations

Indirect Infringement

The complaint seeks a declaratory judgment that Verifone has not infringed "directly or indirectly" (Compl. ¶43). The factual basis for potential indirect infringement allegations by NFE appears to be NFE's lawsuits against Verifone's customers who are the downstream users of the Accused Products (Compl. ¶17).

VII. Analyst’s Conclusion: Key Questions for the Case

  1. Definitional Scope: A central issue for several patents will be one of definitional scope. For the ’201 patent, can the term "detecting a signaling protocol" be construed to cover the configuration of a chip via static logic levels on its pins? For the ’071 patent, can a single "IRQ pin" be construed as an "external bus"?
  2. Mismatch in Technical Operation: The case presents a fundamental question of technical mismatch. Does the accused NXP PN512 component—a near-field communication front-end—actually perform the specific functions of protocol detection (’201 patent), real-time I/O processing (’071 patent), USB endpoint configuration (’350 patent), and power management (’727 patent) in the manner claimed, or are NFE's infringement theories based on a mischaracterization of the chip's operation?
  3. Prior Art and Validity: Verifone has put the validity of all five patents at issue, identifying specific prior art references for each (e.g., Compl. ¶129, ¶143, ¶157, ¶172, ¶185). A key question will be whether these references, particularly the PN511 specification alleged to be prior art to the PN512 for the '531 patent, teach every element of the asserted claims. The complaint includes a revision history table from the PN511 specification indicating it was publicly changed in February 2004 (Compl. p. 44).