DCT
8:23-cv-02186
Huang v. HFC Semiconductor Corp.
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Xiaohua Huang (California)
- Defendant: HFC Semiconductor Corp. (China)
- Plaintiff’s Counsel: Pro Se
- Case Identification: 8:23-cv-02186, M.D. Fla., 09/27/2023
- Venue Allegations: Venue is asserted on the basis that the Defendant is a foreign company, which may be sued in any judicial district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor intellectual property (IP) and integrated circuit (IC) chips infringe a patent related to hierarchical priority encoding logic and circuits.
- Technical Context: The technology concerns specialized logic circuits used in high-speed memory, such as content-addressable memory (CAM), to efficiently determine the highest-priority "hit" among multiple matching data entries.
- Key Procedural History: The patent-in-suit is a reissue patent, which indicates it underwent a post-issuance proceeding at the USPTO to correct an error in the original patent. The complaint does not specify the nature of the correction.
Case Timeline
| Date | Event |
|---|---|
| 2004-03-04 | U.S. Patent No. RE45,259 Priority Date (Provisional App.) |
| 2014-11-25 | U.S. Patent No. RE45,259 Issued |
| 2023-09-27 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Reissue Patent No. RE45,259 - "Hit Ahead Hierarchical Scalable Priority Encoding Logic and Circuits"
The Invention Explained
- Problem Addressed: In content addressable memory, searching can result in multiple matches ("multi-hit"). Conventional logic for selecting the single highest-priority match becomes slow and complex as the number of memory entries grows very large (e.g., into the thousands or millions), creating a performance bottleneck (’259 Patent, col. 1:24-41, 1:58-62).
- The Patented Solution: The patent discloses a "multi-level hierarchical" approach to solve this problem. Instead of processing all hits serially, the system is broken into smaller blocks, each with its own local priority encoder. A key feature is "Hit Ahead Priority Encoding (HAPE)," where a simple "hit" signal is generated and passed to the next level of the hierarchy before the full, more complex binary address of that hit is calculated. This "hit ahead" signal allows the next level to begin its own priority calculation earlier, reducing overall processing time (’259 Patent, Abstract; col. 2:6-14). Figure 2a illustrates this multi-level structure, where local hit logic (201), priority logic (202), and encoding logic (203) feed into a higher-level priority determination (206, 207).
- Technical Importance: This architecture aims to improve the speed, scalability, and design flexibility of priority encoding circuits, which are critical components in high-performance networking and search-engine hardware (’259 Patent, col. 2:3-6).
Key Claims at a Glance
- The complaint asserts "at least claim 29" of the ’259 Patent (Compl. ¶¶ 6, 7, 11).
- Independent Claim 29 recites the following essential elements for a CAM system:
- A circuit segment configured to generate an output based on whether at least one of its inputs corresponds to a first logic level.
- The circuit segment is also configured to set a node to a second logic level in response to an input signal, and subsequently change the node to a third logic level in response to the plurality of inputs.
- The circuit segment output corresponds to the third logic level.
- The complaint does not specify assertion of any dependent claims but makes general allegations of infringement of "one or more of the claims" (Compl. ¶11).
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are identified as "MRAM IP and chips," as well as "CAM, SRAM, eFuse and MRAM IP and chip" that are allegedly developed, used, made, and sold by Defendant HFC (Compl. ¶¶ 6, 7, 11).
Functionality and Market Context
The complaint alleges that these products contain "circuit and logic" and a "function of reading and writing data and information" that "read the claim 29" of the patent (Compl. ¶¶ 6, 12). No specific product names, model numbers, or detailed descriptions of the accused circuitry's operation are provided. The complaint alleges the accused devices have been "designed and used by HFC in its office at 17 Computer Drive West Albany, NY 12205, USA" (Compl. ¶8). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint provides only high-level, conclusory allegations of infringement without a detailed element-by-element mapping. The following chart summarizes the infringement theory as can be construed from the pleading.
RE45,259 Infringement Allegations
| Claim Element (from Independent Claim 29) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a circuit segment configured to generate a circuit segment output based on whether at least one of a plurality of circuit segment inputs received by the circuit segment corresponds to a first logic level, | The accused products contain "circuit and logic" that infringes the claim (Compl. ¶8). | ¶¶ 7, 8 | col. 14:50-54 |
| the circuit segment configured to set a node to a second logic level in response to an input signal, and to subsequently change the node to a third logic level in response to the plurality of circuit segment inputs, | The complaint alleges the accused products contain "the IC with the function which read the claim 29" (Compl. ¶7). | ¶7 | col. 14:55-59 |
| the circuit segment output corresponding to said third logic level. | The complaint does not provide sufficient detail for analysis of this element. | N/A | col. 14:60-61 |
Identified Points of Contention
- Evidentiary Questions: The complaint's primary challenge is its lack of factual detail. A central question will be whether Plaintiff can produce evidence demonstrating that the accused MRAM, SRAM, and other IP cores actually perform the specific operations recited in Claim 29, particularly the two-step "set... and to subsequently change" of a node's logic level.
- Technical Questions: Does the "function of reading and writing data" alleged in the complaint (Compl. ¶12) equate to the dynamic pre-charge and discharge logic described in the patent's preferred embodiments (e.g., ’259 Patent, Fig. 4, col. 5:42-65) and seemingly required by the language of Claim 29? The complaint does not offer evidence to connect these functionalities.
V. Key Claim Terms for Construction
- The Term: "circuit segment"
- Context and Importance: This term defines the fundamental building block of Claim 29. Its construction is critical because it will determine whether the claim is limited to the specific type of dynamic logic circuits disclosed in the patent or if it can be read more broadly to cover other logic structures found in Defendant's accused IP cores. Practitioners may focus on this term because the infringement case depends on whether Defendant's standard memory circuits can be considered a "circuit segment" as claimed.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term itself is generic. The patent claims are not limited to a specific type of memory, and the specification discusses the invention's applicability to priority encoding in a general sense, which could support an interpretation not strictly tied to one embodiment (’259 Patent, col. 1:16-20).
- Evidence for a Narrower Interpretation: Claim 29 recites a specific functional behavior for the "circuit segment": "to set a node to a second logic level... and to subsequently change the node to a third logic level." This language strongly suggests a dynamic, two-phase (e.g., pre-charge/evaluate) operation. The specification's only detailed embodiments show dynamic NOR logic circuits that perform this function (’259 Patent, Fig. 4-7; col. 5:42-65). A party could argue that "circuit segment" is therefore limited to this class of dynamic circuits.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement, stating that HFC induced its customers to infringe by "using the devices" for "reading and writing data" and that these devices are not staple articles of commerce suitable for substantial non-infringing use (Compl. ¶12). The factual basis for knowledge or intent to induce is not detailed.
- Willful Infringement: The complaint does not use the term "willful" and does not plead any specific facts regarding Defendant's pre- or post-suit knowledge of the patent or its alleged infringement that would typically support a claim for willfulness.
VII. Analyst’s Conclusion: Key Questions for the Case
- Evidentiary Sufficiency: A threshold issue for the court will be whether the plaintiff's conclusory allegations are sufficient to state a plausible claim for relief. The case will depend on whether the plaintiff can later produce specific, technical evidence mapping the actual operation of the accused HFC products to the distinct logical steps recited in Claim 29.
- Definitional Scope: The dispute may turn on a question of claim construction: can the term "circuit segment", as defined by the claim language requiring a two-step "set-and-change" node operation and taught in the patent's dynamic logic embodiments, be interpreted to read on the allegedly infringing logic within Defendant's semiconductor IP products?
- Functionality Mismatch: A core technical question will be one of operational correspondence. Does the general "function of reading and writing data" in a memory chip, as alleged in the complaint, inherently perform the specialized, multi-stage "hit ahead priority encoding" function that is the specific focus of the ’259 Patent?