Altair Logix LLC v. Swiss Bionic Solutions USA Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Swiss Bionic Solutions USA, Inc. (Florida)
  • Plaintiff’s Counsel: Sand, Sebolt & Wernow Co., LPA
• Case Identification: 0:19-cv-61919, S.D. Fla., 07/30/2019
• Venue Allegations: Venue is alleged to be proper in the Southern District of Florida because the Defendant is a Florida corporation and has allegedly committed acts of infringement in the district.
• Core Dispute: Plaintiff alleges that Defendant’s Omnium1 tablet, which incorporates a multi-core processor, infringes a patent related to dynamically reconfigurable circuits for media processing.
• Technical Context: The technology concerns system-on-a-chip processor architectures designed to offer the performance of fixed-function hardware with the flexibility of programmable devices for media-rich applications.
• Key Procedural History: The complaint notes that Claim 1 of the asserted patent was an originally filed claim that issued without amendment, a fact that may be relevant to future claim construction arguments by potentially limiting the relevance of the prosecution history.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates

• Patent Identification: U.S. Patent No. 6,289,434, "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates," issued September 11, 2001.

The Invention Explained

• Problem Addressed: The patent addresses the trade-offs between performance, cost, and flexibility in integrated circuit design. It describes traditional hard-wired, "fixed-function" circuits as high-performing but inflexible and costly due to "temporal redundancy"—the need to implement all possible functional requirements on silicon, even those not in use at a given moment (’434 Patent, col. 2:50-57; Compl. ¶19). Conversely, alternative approaches like general-purpose microprocessors, DSPs, and FPGAs were described as suffering from either performance or cost-effectiveness limitations for complex, real-time media tasks (’434 Patent, col. 2:1-33; Compl. ¶¶14-16).
• The Patented Solution: The invention proposes an apparatus of dynamically reconfigurable "media processing units" (MPUs) that can adapt their configuration at run-time based on varying input data and processing requirements (’434 Patent, col. 3:6-11). This solution aims to reduce cost by removing redundancy through the re-use of computational and storage elements in different configurations, while maintaining performance comparable to fixed-function implementations (Compl. ¶20). The overall architecture, depicted in Figure 3, shows multiple MPUs interconnected through a memory-mapped protocol (’434 Patent, Fig. 3).
• Technical Importance: The technology represents an effort to create a hybrid processor architecture that could deliver the high performance of application-specific integrated circuits (ASICs) with the adaptability of programmable processors for the growing field of digital media processing (’434 Patent, col. 2:64–col. 3:1).

Key Claims at a Glance

• The complaint asserts independent Claim 1 (’434 Patent, col. 55:21–col. 56:33; Compl. ¶26).
• Claim 1 recites an apparatus for processing data comprising:
  • An addressable memory for storing data and instructions.
  • A plurality of media processing units, each having an input/output coupled to the memory.
  • Each media processing unit comprises a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit.
  • The ALU must be capable of operating concurrently with the multiplier and arithmetic unit.
  • The bit manipulation unit must be capable of operating concurrently with the ALU and at least one of the multiplier or the arithmetic unit.
  • Each of the media processing units must be capable of performing an operation simultaneously with other media processing units.
  • An "operation" is defined as receiving an instruction and data from memory, processing the data to produce a result, and providing the result to the media processor input/output.

III. The Accused Instrumentality

Product Identification

• The Omnium1 tablet ("Accused Instrumentality") (Compl. ¶26).

Functionality and Market Context

• The complaint alleges that the Omnium1 tablet contains a Rockchip RK3188 system-on-a-chip, which includes a quad-core ARM Cortex-A9 processor (Compl. ¶28, p. 11). The complaint’s infringement theory identifies these multiple ARM Cortex-A9 cores as the claimed "plurality of media processing units" (Compl. ¶28). The functionality of the claimed multiplier, arithmetic unit, ALU, and bit manipulation unit is alleged to be performed by the NEON media coprocessor integrated within each ARM processor core (Compl. ¶¶29-32). The complaint provides a block diagram of the RK3188 processor to illustrate its multi-core architecture (Compl. p. 11, Fig. 1.3). It also provides a diagram illustrating the functional blocks within the NEON coprocessor, such as the "Integer MUL" and "Integer ALU" (Compl. p. 15). The complaint does not provide sufficient detail for analysis of the product's commercial importance or market positioning.

IV. Analysis of Infringement Allegations

'434 Patent Infringement Allegations

• Identified Points of Contention:
  • Scope Questions: A central dispute may concern the definition of "media processing unit". The defense may argue that this term, in the context of the patent, refers to the novel, run-time reconfigurable architecture described in the specification and does not read on a standard, off-the-shelf ARM Cortex-A9 processor core, which it might characterize as the type of prior art the invention sought to improve upon.
  • Technical Questions: The claim requires specific modes of concurrent operation between the ALU, bit manipulation unit, multiplier, and arithmetic unit. The complaint alleges this concurrency exists "upon information and belief" (Compl. ¶¶31, 32). A key factual question will be whether the accused NEON coprocessor's functional units are, in fact, "capable of operating concurrently" in the specific manner required by the claim, which may require detailed evidence beyond the high-level block diagrams provided.

V. Key Claim Terms for Construction

• The Term: "media processing unit"

• Context and Importance: This term is foundational to the patent, and its construction will likely determine whether an off-the-shelf, general-purpose processor core like the ARM Cortex-A9 can be an infringing structure. Practitioners may focus on this term because the plaintiff's case depends on equating this term with the accused ARM cores, while the patent's specification heavily emphasizes a novel, reconfigurable architecture.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The patent states that the "aggregate of the dynamically reconfigurable computational and storage elements will heretofore be referred to as a 'media processing unit'" ('434 Patent, col. 3:14-18). The patent also describes the unit as comprising a multiplier, ALU, and bit manipulation unit, functions present in many modern processors.
  • Evidence for a Narrower Interpretation: The "Summary of the Invention" and "Background" sections frame the invention as a solution to the inflexibility and cost of prior art systems, achieved by "adaptively dynamically reconfiguring groups of computational and storage elements" ('434 Patent, col. 3:9-13). The defense could argue a "media processing unit" must possess this specific dynamic, run-time reconfigurability, a feature not explicitly alleged to be present in the ARM Cortex-A9 core.

• The Term: "capable of operating concurrently"

• Context and Importance: This phrase appears twice in Claim 1 to define the required operational relationship between the internal components of a "media processing unit". Infringement will depend on whether the alleged components of the NEON coprocessor exhibit this specific type of concurrency.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term could be interpreted to mean that the functional units can be active in different stages of a pipeline in the same clock cycle, a common feature in modern processors.
  • Evidence for a Narrower Interpretation: The specification states that the claimed architecture may "execute three concurrent 32 bit arithmetic or logical operations in parallel while accessing four 32 bit data words from memory... all this in a single clock cycle" ('434 Patent, col. 4:39-44). This language may support an argument that "concurrently" requires a specific form of parallel execution beyond standard pipelining, and the court will have to determine if the accused device's operation meets this potentially higher bar.

VI. Other Allegations

The complaint does not contain allegations for indirect infringement or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "media processing unit", which is described in the patent as a novel, run-time reconfigurable architecture, be construed to cover a standard, off-the-shelf ARM Cortex-A9 processor core? The outcome of this claim construction will be critical to the infringement analysis.
• A key evidentiary question will be one of technical operation: does the accused NEON coprocessor in the Rockchip RK3188 processor in fact meet the specific "concurrency" limitations of Claim 1? The case will likely require detailed technical evidence to establish whether the multiplier, arithmetic unit, ALU, and bit manipulation unit are "capable of operating concurrently" in the precise manner mandated by the claim.