DCT
1:19-cv-05313
Altair Logix LLC v. Winmate Communications US Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: Winmate Communications US, Inc. (Georgia)
- Plaintiff’s Counsel: Hill Kertscher & Wharton LLP
- Case Identification: 1:19-cv-05313, N.D. Ga., 11/22/2019
- Venue Allegations: Venue is alleged to be proper as Defendant is a Georgia corporation with an established and principal place of business within the Northern District of Georgia.
- Core Dispute: Plaintiff alleges that Defendant’s HMI/ARM Panel PCs, which incorporate certain multicore processors, infringe a patent related to dynamically reconfigurable circuits for media processing.
- Technical Context: The technology concerns system-on-a-chip (SoC) architectures that use reconfigurable processing units to improve performance and lower costs for computationally intensive tasks like video and graphics processing.
- Key Procedural History: The complaint notes that claim 1 of the asserted patent was an originally filed claim that issued without amendment or a prior art rejection during prosecution.
Case Timeline
| Date | Event |
|---|---|
| 1997-02-28 | '434 Patent Priority Date |
| 2001-09-11 | '434 Patent Issue Date |
| 2015-01-02 | Earliest known date of Accused Product marketing |
| 2019-11-22 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates"
The Invention Explained
- Problem Addressed: The patent describes the trade-offs inherent in prior art integrated circuit design. Hard-wired, fixed-function circuits offer high performance but are inflexible and suffer from "temporal redundancy," where specialized silicon is idle when not in use. Conversely, more flexible solutions like general-purpose microprocessors, DSPs, and FPGAs often sacrifice performance or cost-effectiveness for media-intensive, real-time tasks (Compl. ¶¶13-19; ’434 Patent, col. 1:42–2:39).
- The Patented Solution: The invention proposes an apparatus with multiple "media processing units" (MPUs) on a single chip. These MPUs are composed of computational and storage elements that can be dynamically reconfigured at run-time to adapt to varying data and processing requirements. By re-using these elements in different configurations, the system aims to reduce redundancy and cost while achieving performance comparable to fixed-function implementations (Compl. ¶¶20-21; ’434 Patent, col. 3:1-11). The architecture, depicted in the patent’s Figure 3, connects these MPUs through a memory-mapped communication protocol (Compl. ¶23).
- Technical Importance: This architecture represents an approach to creating powerful and efficient Systems-on-a-Chip (SoCs) that blend the performance of dedicated hardware with the flexibility of programmable processors, a key challenge in the evolution of devices for multimedia applications (Compl. ¶12, ¶20).
Key Claims at a Glance
- The complaint asserts direct infringement of at least independent claim 1 (Compl. ¶26).
- The essential elements of independent claim 1 are:
- An addressable memory for storing data and instructions with a plurality of inputs/outputs.
- A plurality of media processing units, each coupled to the memory.
- Each media processing unit comprises: a multiplier; an arithmetic unit; an arithmetic logic unit capable of operating concurrently with the multiplier and/or arithmetic unit; and a bit manipulation unit capable of operating concurrently with the arithmetic logic unit and the multiplier and/or arithmetic unit.
- Each of the plurality of media processors is for performing at least one operation simultaneously with other media processing units.
- Each operation comprises receiving instructions and data from memory, processing the data, and providing a result.
- The prayer for relief reserves the right to assert other claims (Compl. ¶35.a).
III. The Accused Instrumentality
Product Identification
The complaint identifies Defendant’s HMI/ARM Panel PC product line as the Accused Instrumentality (Compl. ¶26). The allegations focus on models that incorporate processors from the Freescale (now NXP) i.MX 6 series, such as the i.MX 6DualLite (Compl. pp. 14, 16).
Functionality and Market Context
The accused products are described as Human-Machine Interface (HMI) panel computers designed for automation applications (Compl. p. 14). The complaint alleges that the dual-core ARM Cortex-A9 processors within the i.MX 6 chip function as the claimed "plurality of media processing units" (Compl. ¶28). The infringement theory centers on the functionality of the NEON media coprocessor integrated into each ARM core, which is alleged to perform the claimed data processing operations (Compl. ¶28). The complaint includes a block diagram of the i.MX 6DualLite processor, highlighting its dual ARM Cortex-A9 cores and the "NEON Per Core" feature (Compl. p. 17).
IV. Analysis of Infringement Allegations
Claim Chart Summary
The complaint provides a detailed, element-by-element infringement theory for claim 1. The core allegations are summarized below.
’434 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an addressable memory for storing the data, and a plurality of instructions... | The Accused Instrumentality contains a memory system (e.g., 1GB DDR3) coupled to multicore ARM processors via multiple inputs/outputs. | ¶27 | col. 55:21-26 |
| a plurality of media processing units, each media processing unit having an input/output coupled to...memory... | The Accused Instrumentality's i.MX 6 processor contains dual ARM Cortex-A9 processors, which are identified as the "media processing units." This is shown in a processor block diagram. | ¶28, p. 17 | col. 55:27-30 |
| a multiplier having a data input...an instruction input...and a data output... | Each ARM processor contains a NEON media coprocessor that includes a multiplier (Integer MUL or FP MUL), as shown in a NEON pipeline diagram. | ¶29, p. 22 | col. 55:31-36 |
| an arithmetic unit having a data input...an instruction input...and a data output... | The NEON media coprocessor includes an arithmetic unit (e.g., an FP ADD), as shown in the NEON pipeline diagram. | ¶30, p. 22 | col. 55:37-42 |
| an arithmetic logic unit...capable of operating concurrently with at least one selected from the multiplier and arithmetic unit; | The NEON media coprocessor contains an arithmetic logic unit (e.g., an Integer ALU) alleged to be capable of concurrent operation with the other units. | ¶31, p. 25 | col. 55:43-50 |
| and a bit manipulation unit...capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit; | The NEON media coprocessor contains an integer shift unit, identified as the bit manipulation unit, which is alleged to be capable of concurrent operation. | ¶32, p. 27 | col. 55:51-56:4 |
| each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units... | The dual ARM Cortex-A9 processors on the i.MX 6 chip are alleged to perform operations simultaneously. The processor's block diagram shows the dual-core structure. | ¶33, p. 28 | col. 56:5-8 |
| each operation comprising: receiving...instruction and data from the memory, processing the data...and providing...at least one result... | Each ARM Cortex-A9 media processor is alleged to receive instructions and data from memory via its NEON coprocessor, process it, and produce a result. | ¶¶34-35 | col. 56:9-17 |
Identified Points of Contention
- Scope Questions: A central issue may be whether the term "media processing unit"—described in the patent as an "aggregate of the dynamically reconfigurable computational and storage elements" (Compl. ¶21)—can be construed to read on a general-purpose ARM Cortex-A9 CPU core. The patent emphasizes reconfigurability to reduce redundancy, which raises the question of whether a standard, fixed-pipeline CPU core meets this definition.
- Technical Questions: The claim requires that the arithmetic logic unit and bit manipulation unit be "capable of operating concurrently" with other specified units. The complaint supports this with block diagrams showing separate functional units in the NEON pipeline (Compl. p. 25). However, a key question for the court will be what level of proof is required to demonstrate this "concurrent" capability—whether the mere existence of separate hardware blocks suffices, or if evidence of true parallel execution within the microarchitecture is necessary.
V. Key Claim Terms for Construction
The Term: "media processing unit"
Context and Importance: This term is the foundational building block of the claimed apparatus. Its construction is critical because it will determine whether a general-purpose processor core like the accused ARM Cortex-A9 falls within the scope of the claims.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent’s abstract describes processors that perform arithmetic, logic, and bit manipulation functions, a general description that could encompass an ARM core with a NEON coprocessor (’434 Patent, Abstract). The complaint leverages this by identifying the entire ARM Cortex-A9 processor as the claimed unit (Compl. ¶28).
- Evidence for a Narrower Interpretation: The specification explicitly defines the invention as an apparatus for "adaptively dynamically reconfiguring groups of computations and storage elements" to remove "temporal redundancy" (Compl. ¶¶19, 21; ’434 Patent, col. 2:50-53, col. 3:14-18). Practitioners may focus on this language to argue that a "media processing unit" must possess a specific reconfigurable hardware fabric, distinct from the fixed pipeline of a conventional CPU core.
The Term: "concurrently"
Context and Importance: This term defines the required operational relationship between the functional sub-units (ALU, multiplier, bit manipulation unit) within each "media processing unit". Infringement of these limitations depends on the functional capabilities of the accused NEON coprocessor.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not provide a specific definition of "concurrently." A party could argue it means the units are simply capable of being active in overlapping pipeline stages, a feature common in modern processors. The complaint’s reliance on block diagrams showing distinct units suggests such an interpretation (Compl. p. 25).
- Evidence for a Narrower Interpretation: The claim language requires capability of concurrent operation between specific units (e.g., the bit manipulation unit operating concurrently with the ALU and at least one of the multiplier or arithmetic unit) (’434 Patent, col. 55:54-56:4). A party could argue this implies true, simultaneous, and independent operation, requiring a higher evidentiary standard than simply co-existing in a pipeline.
VI. Other Allegations
The complaint does not contain counts for indirect or willful infringement. It alleges only direct infringement and asserts that Defendant had at least constructive notice of the patent (Compl. ¶¶26, 37).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "media processing unit", rooted in the patent’s context of "dynamically reconfigurable" hardware designed to eliminate redundancy, be construed to cover a standard, general-purpose CPU core (ARM Cortex-A9) with a fixed-pipeline SIMD coprocessor (NEON)?
- A key evidentiary question will be one of functional capability: does the accused NEON coprocessor's architecture support the specific "concurrent" operations between its multiplier, ALU, and bit manipulation units as mandated by claim 1? The resolution will likely depend on technical evidence of the processor's microarchitectural operation, beyond the high-level block diagrams presented in the complaint.