DCT

1:22-cv-00282

Katana Silicon Tech LLC v. Micron Technology Inc

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:22-cv-00214, W.D. Tex., 03/04/2022
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants maintain a regular and established place of business in the district, specifically a regional office and design center in Austin, and have committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s high-density memory products infringe patents related to semiconductor chip packaging structures and manufacturing methods for creating stacked, multi-chip modules.
  • Technical Context: The technology concerns methods for vertically stacking multiple semiconductor chips within a single package to increase memory capacity and performance while minimizing physical footprint, a critical technology for modern portable electronics and data storage.
  • Key Procedural History: The complaint alleges that Plaintiff provided Defendants with notice of the asserted patents via letters dated August 22, 2018, and September 18, 2018, which may be relevant to the allegations of willful infringement.

Case Timeline

Date Event
1998-01-14 Earliest Priority Date for '806 and '879 Patents
2000-06-28 Earliest Priority Date for '013 Patent
2002-03-05 U.S. Patent No. 6,352,879 Issues
2004-05-04 U.S. Patent No. 6,731,013 Issues
2005-10-04 U.S. Patent No. RE38,806 Issues
2018-08-22 Plaintiff's first alleged notice letter to Defendants
2018-09-18 Plaintiff's second alleged notice letter to Defendants
2022-03-04 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Reissue Patent No. RE38,806 - "SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME"

  • Patent Identification: RE38,806, "SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME," issued October 4, 2005.
  • The Invention Explained:
    • Problem Addressed: The patent describes a market need for semiconductor packages that are even smaller and denser than existing stacked-package devices, requiring a combination of a stacked-package structure and a Chip Size Package (CSP) structure ('806 Patent, col. 2:10-15). Prior art methods using adhesive pastes could lead to overflow that interfered with wire bonding, while methods using separate thermo-compression sheets required multiple, precise positioning steps, complicating manufacturing ('806 Patent, col. 2:20-53).
    • The Patented Solution: The invention is a semiconductor device with at least two stacked chips where each chip has an insulating adhesion layer pre-applied to its back surface. A second chip is mounted on the front (circuit) surface of a first chip. This pre-application of the adhesive simplifies the manufacturing process to a single positioning step for each chip and allows wire bonds to be placed closer to the chip edges, enabling a more compact final package ('806 Patent, col. 3:28-44).
    • Technical Importance: This approach enabled the creation of smaller, higher-density multi-chip modules, a key factor in the miniaturization and increased capacity of memory products for portable electronics (Compl. ¶26).
  • Key Claims at a Glance:
    • The complaint asserts infringement of at least independent claim 1 (Compl. ¶32).
    • Essential elements of claim 1 include:
      • An insulating substrate including a wiring layer with electrode sections.
      • A first semiconductor chip with a first insulating adhesion layer on its back surface, mounted on the wiring layer.
      • A second semiconductor chip with a second insulating adhesion layer on its back surface, mounted on the circuit-formed front surface of the first chip.
      • Each chip is wire-bonded to the electrode section, and the entire assembly is sealed with a resin.

U.S. Patent No. 6,352,879 - "SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME"

  • Patent Identification: 6,352,879, "SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME," issued March 5, 2002.
  • The Invention Explained:
    • Problem Addressed: The '879 Patent addresses the same technical problem as the '806 Patent: the need for a simplified manufacturing process for creating miniaturized, high-density stacked-chip packages ('879 Patent, col. 1:53-63). The patent notes that conventional methods for bonding chips together were complex and could hinder miniaturization efforts ('879 Patent, col. 2:12-42).
    • The Patented Solution: The invention is a method of manufacturing a stacked semiconductor device. The key steps involve forming an insulating adhesion layer on the back surface of a semiconductor wafer, dicing the wafer into individual chips, and then mounting the chips. This process is repeated for a second wafer, with the second set of chips mounted on top of the first. By applying the adhesive at the wafer level, the method simplifies subsequent assembly ('879 Patent, col. 4:21-51).
    • Technical Importance: This wafer-level application of adhesive simplified the assembly of stacked-chip packages, making the production of high-density memory more efficient and reliable (Compl. ¶58-59).
  • Key Claims at a Glance:
    • The complaint asserts infringement of at least independent claim 1 (Compl. ¶63).
    • Essential steps of method claim 1 include:
      • Forming a first adhesion layer on the back surface of a first wafer.
      • Producing first semiconductor chips by dicing the first wafer.
      • Mounting the first chips on a wiring layer.
      • Forming a second adhesion layer on the back surface of a second wafer.
      • Producing second semiconductor chips by dicing the second wafer.
      • Mounting the second chips on the first chips.
      • Wire-bonding both chips to the wiring layer and sealing the assembly.

U.S. Patent No. 6,731,013 - "WIRING SUBSTRATE, SEMICONDUCTOR DEVICE AND PACKAGE STACK SEMICONDUCTOR DEVICE"

  • Patent Identification: U.S. Patent No. 6,731,013, "WIRING SUBSTRATE, SEMICONDUCTOR DEVICE AND PACKAGE STACK SEMICONDUCTOR DEVICE," issued May 4, 2004.
  • Technology Synopsis: This patent addresses electrical connection failures in wire bonding caused by the deformation of the thin insulating substrate when pressure is applied to the terminal section (Compl. ¶90). The patented solution is a wiring substrate that includes a "support pattern" on the surface opposite from, and corresponding in position to, the terminal section, which provides mechanical support to prevent deformation and ensure reliable bonding ('013 Patent, Abstract; Compl. ¶91).
  • Asserted Claims: At least independent claim 11 is asserted (Compl. ¶96).
  • Accused Features: The accused products are alleged to be semiconductor devices incorporating a wiring substrate with a terminal section, land section, and a support pattern that improves wire bonding, thereby infringing the '013 Patent (Compl. ¶97-104).

III. The Accused Instrumentality

Product Identification

The complaint identifies a range of Micron's memory products, including NAND flash memories, LPDDR4, and LPDDR5 DRAM (Compl. ¶30, ¶61, ¶94). The "MT29F768G08EEHBBJ4 32L 3D NAND Flash Memory semiconductor device" is named as the "Exemplary Accused Product" for all three patents (Compl. ¶32, ¶63, ¶96).

Functionality and Market Context

The accused products are high-density semiconductor memory components. The complaint alleges these products achieve their high density through a stacked-package structure where multiple semiconductor dies are layered vertically within a single package (Compl. ¶33). These components are sold for use in a wide array of consumer and enterprise electronics, such as smartphones, solid-state drives (SSDs), and personal computers (Compl. ¶9, ¶26). The complaint includes a cross-sectional scanning electron microscope (SEM) image allegedly of the Exemplary Accused Product, depicting two stacked semiconductor dies labeled "NAND DIE 1" and "NAND DIE 2" (Compl. ¶33, Fig. 1).

IV. Analysis of Infringement Allegations

RE38,806 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
an insulating substrate (A) including a wiring layer (B) having electrode sections (C) The product contains an insulating substrate with a wiring layer and electrode sections, as shown in annotated X-ray and SEM images. ¶33 col. 4:1-3
a first semiconductor chip (D) having a first insulating adhesion layer (E) adhered to its back surface (F) where a circuit is not formed (G), said first semiconductor chip being mounted on said wiring layer... (H) A first semiconductor die ("NAND DIE 1") is mounted on the wiring layer, allegedly attached via a first adhesion layer applied to its non-circuit back surface. A cross-sectional SEM image is provided as evidence (Compl. ¶34, Fig. 2). ¶34 col. 4:4-10
a second semiconductor chip (I) having a second insulating adhesion layer (J) adhered to its back surface (K) where a circuit is not formed (L), said second semiconductor chip being mounted on a circuit-formed front surface of said first semiconductor chip... (M) A second semiconductor die ("NAND DIE 2") is mounted on the front surface of the first die, allegedly attached via a second adhesion layer applied to its non-circuit back surface. A cross-sectional SEM image is provided as evidence (Compl. ¶35, Fig. 3). ¶35 col. 4:11-18
each of said first and second semiconductor chips being wire-bonded to the electrode section with a wire (N), said first and second semiconductor chips and the wire being sealed with a resin (O) The first and second dies are shown wire-bonded to the substrate's electrode sections, with the entire assembly encapsulated in a resin. An X-ray image is provided as evidence showing the wires and resin sealing (Compl. ¶36, Fig. 4). ¶36 col. 4:19-24

6,352,879 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
(a) forming a first adhesion layer on a back surface of a first wafer... (b) producing separate first semiconductor chips from said first wafer by dicing The complaint alleges the accused product is made by a method that includes forming an adhesion layer on a wafer's back surface, then dicing it into chips. A visual showing the alleged result of the dicing step is provided (Compl. ¶65, Fig. 2). ¶64-65 col. 4:22-28
(c) mounting said first semiconductor chips on a wiring layer with the back surface of the first semiconductor chip facing said wiring layer The first chips are allegedly mounted on a wiring layer with their back surfaces facing the layer. An annotated SEM image depicts this alleged final arrangement (Compl. ¶66, Fig. 3). ¶66 col. 4:29-31
(d) forming a second adhesion layer on a back surface of a second wafer... (e) producing separate second semiconductor chips from said second wafer by dicing The method allegedly repeats the process for a second wafer, forming an adhesion layer and then dicing it into a second set of chips. A visual shows the alleged result of the second dicing step (Compl. ¶68, Fig. 5). ¶67-68 col. 4:32-38
(f) mounting said second semiconductor chip on said first semiconductor chip... (g) wire-bonding... (h) wire-bonding... and (i) sealing... The second chips are allegedly mounted on the first chips, and the entire assembly is wire-bonded and sealed. The complaint alleges the final product is made by this method, with an image showing the final mounted configuration (Compl. ¶69, Fig. 6). ¶69 col. 4:39-51

Identified Points of Contention

  • Scope Questions: A central question for the '879 method patent will be evidentiary. The complaint's evidence is based on reverse engineering of a finished product. This raises the question of what direct evidence Plaintiff can obtain to prove that Micron's manufacturing process follows the specific sequence of steps claimed, particularly the application of an "adhesion layer" at the wafer level before dicing.
  • Technical Questions: For the '806 apparatus patent, the dispute may focus on whether the material between the stacked dies in the accused product constitutes an "insulating adhesion layer" as contemplated by the patent. The patent contrasts its solution with prior art adhesive pastes and separately-positioned thermo-compression sheets, which may create a point of contention regarding the specific nature and application method of the layer in the accused product. For the '013 patent, a question is whether the structure identified as a "support pattern" in the accused product actually performs the function of improving wire bonding reliability, or if it is a structure present for unrelated design or manufacturing reasons.

V. Key Claim Terms for Construction

For U.S. RE38,806 and U.S. 6,352,879

  • The Term: "insulating adhesion layer" / "adhesion layer"
  • Context and Importance: This term is the technological core of both the '806 and '879 patents. Its construction will be critical for determining infringement. The patents distinguish their invention from prior art methods like potting with adhesive paste or using separately-positioned thermo-compression sheets. Practitioners may focus on this term because the dispute will likely center on whether the material and method used by Micron fall within the scope of this term, or if they align more with a known prior art technique.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claims themselves use the general term "adhesion layer" without specifying its composition or method of application (e.g., '806 Patent, col. 3:5-9). This may support a construction that is not limited to a specific material, such as a thermo-compression sheet.
    • Evidence for a Narrower Interpretation: The specification repeatedly emphasizes that the adhesion layer is "in advance disposed on the back surfaces of the first and second semiconductor chips" ('806 Patent, col. 3:37-39). The method claims of the '879 patent explicitly require forming the layer on the "wafer" before dicing ('879 Patent, col. 4:22-28). This could support a narrower construction requiring the layer to be pre-applied at the wafer-level, even for the '806 apparatus claims, to distinguish the invention from prior art where adhesive is applied to individual chips during package assembly.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges that Defendants induced infringement by providing customers and end-users with "data sheets, technical guides, demonstrations, ... product specifications, [and] user manuals" that allegedly instruct on making and using the infringing products with the specific intent to cause infringement (Compl. ¶44-46, ¶77-79, ¶112-114). It further alleges contributory infringement, stating the accused products are not staple commodities and are especially made or adapted for use in an infringing manner (Compl. ¶45, ¶78, ¶113).
  • Willful Infringement: Willfulness is alleged based on Defendants' purported pre-suit knowledge of the patents. The complaint cites notice letters sent to Defendants on August 22, 2018, and September 18, 2018 (Compl. ¶37, ¶70, ¶105). The complaint also asserts that Defendants have "intimate knowledge of the art" due to their own extensive patent portfolio in the same technology area, suggesting infringement was known or obvious (Compl. ¶39, ¶72, ¶107).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of evidentiary proof: For the '879 method patent, can Plaintiff develop evidence beyond reverse engineering to demonstrate that Micron’s confidential manufacturing process actually performs the claimed sequence of applying an "adhesion layer" at the wafer level prior to dicing, or will the analysis be limited to inferences from the final product's structure?
  • A second central question will be one of claim scope: For the '806 apparatus patent, how will the term "insulating adhesion layer" be construed? Will the court find that the term is limited by the specification's repeated emphasis on pre-application at the wafer stage, or will it adopt a broader meaning that covers any adhesive material found between the stacked chips in the final assembled product?
  • A key technical question for the '013 patent will be one of functionality: Does the accused product's alleged "support pattern" actually perform the claimed function of improving wire bonding by preventing substrate deformation, or is there a fundamental mismatch in its technical purpose and operation?