DCT
1:22-cv-00375
Bell Semiconductor LLC v. Micron Technology Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Micron Technology, Inc. (Idaho)
- Plaintiff’s Counsel: Givens Pursley LLP
- Case Identification: 1:22-cv-00375, D. Idaho, 08/26/2022
- Venue Allegations: Venue is alleged to be proper in the District of Idaho because Defendant Micron has its headquarters and a regular and established place of business in Boise, Idaho, and has allegedly committed acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal semiconductor design processes, used to create its chips, infringe two patents related to improving the efficiency of electronic design automation (EDA) software.
- Technical Context: The technology concerns EDA software methods used to ensure the manufacturability of complex integrated circuits, specifically by improving how designers validate against short circuits and insert "dummy metal" to aid in the manufacturing process.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history between the parties.
Case Timeline
| Date | Event |
|---|---|
| 2003-10-10 | U.S. Patent No. 7,260,803 Priority Date |
| 2004-09-22 | U.S. Patent No. 7,149,989 Priority Date |
| 2006-12-12 | U.S. Patent No. 7,149,989 Issued |
| 2007-08-21 | U.S. Patent No. 7,260,803 Issued |
| 2022-08-26 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,149,989 - Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design (Issued Dec. 12, 2006)
The Invention Explained
- Problem Addressed: The patent describes a dilemma in semiconductor design verification. Performing a full validation check for design faults late in the process is risky; a late-found error could force a costly redesign. However, running a full check early in the process is inefficient, as it requires significant processing time and generates many "false positive" errors because the design is still incomplete. (Compl. ¶24; ’989 Patent, col. 2:40-58).
- The Patented Solution: The invention proposes a focused, early-stage validation method. Instead of using a complete set of design rules, the method generates and uses a "specific rule deck" that only contains rules for identifying a critical type of error: "texted metal short circuits" (i.e., erroneous connections between different named signal lines, like power and ground). This allows for the early detection of fundamental errors without the overhead and noise of a full validation run. (Compl. ¶25; ’989 Patent, col. 3:23-34, Fig. 3).
- Technical Importance: This approach allows design teams to identify and correct significant layout problems, such as in the power distribution map, early in the design cycle, which reduces computer processing time and avoids schedule delays. (Compl. ¶8; ’989 Patent, col. 3:3-11).
Key Claims at a Glance
- The complaint asserts independent claim 1. (Compl. ¶43).
- The essential elements of independent claim 1 are:
- (a) receiving as input a representation of an integrated circuit design;
- (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design;
- (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits between different signal sources in addition to power and ground; and
- (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify the texted metal short circuits.
- The complaint generally alleges infringement of "one or more claims" of the patent. (Compl. ¶42).
U.S. Patent No. 7,260,803 - Incremental Dummy Metal Insertions (Issued Aug. 21, 2007)
The Invention Explained
- Problem Addressed: In semiconductor manufacturing, "dummy metal" is added to empty areas of a chip to ensure uniform polishing during a process called Chemical Mechanical Planarization (CMP). The patent states that prior art methods required the entire dummy metal pattern to be discarded and regenerated from scratch whenever a design was changed (e.g., via an Engineering Change Order, or ECO). This regeneration could delay a project by 30 hours or more for each change. (Compl. ¶33; ’803 Patent, col. 1:47-65).
- The Patented Solution: The patent discloses an incremental method that avoids a full regeneration. After a design change, the process checks to see if any of the pre-existing dummy metal objects now intersect with new or moved design elements. If an intersection is found, only the specific intersecting dummy metal object is deleted, leaving the rest of the dummy fill pattern intact and thereby avoiding the need to rerun the entire tool. (Compl. ¶34; ’803 Patent, col. 2:5-14, Fig. 2).
- Technical Importance: This method significantly reduces the time and computational cost associated with implementing late-stage design changes, helping manufacturers meet aggressive design schedules. (Compl. ¶34; ’803 Patent, col. 2:15-22).
Key Claims at a Glance
- The complaint asserts independent claim 1. (Compl. ¶56).
- The essential elements of independent claim 1 are:
- (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; and
- (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool.
- The complaint generally alleges infringement of "one or more claims" of the patent. (Compl. ¶55).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are the electronic design automation (EDA) processes and methodologies allegedly used by Micron to design its semiconductor devices. (Compl. ¶43, 56). The complaint identifies products manufactured using these alleged processes, such as the Micron 2200 MTFDHBA256TCK-1AS1AABYY 256GB NVMe SSD and its internal T15SB1 controller. (Compl. ¶1, 42).
Functionality and Market Context
- The complaint alleges that Micron employs EDA design tools from vendors such as Cadence, Synopsys, and/or Siemens. (Compl. ¶43, 56). These tools are alleged to perform the patented methods. For the ’989 Patent, the tools are said to include a "short finder" or similar functionality to identify texted metal shorts. (Compl. ¶45). For the ’803 Patent, the tools are alleged to perform incremental dummy metal updates after an Engineering Change Order (ECO) by performing a Design Rule Check (DRC) and trimming or repairing intersecting fill geometries. (Compl. ¶57-58). The complaint asserts these patented methods provide significant commercial value but does not provide specific data on the market position of the resulting products. (Compl. ¶5, 8).
IV. Analysis of Infringement Allegations
’989 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input a representation of an integrated circuit design; | Micron’s accused processes allegedly receive a representation of an IC design, for example by importing a design file into a Synopsys IC Validator tool. | ¶43; Ex. D, p. 64 | col. 6:7-8 |
| (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; | The accused processes allegedly receive a physical design rule deck file containing instructions for the validation tool. | ¶44; Ex. D, p. 65 | col. 6:11-14 |
| (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits... | Micron’s accused processes allegedly employ tools with a "short finder" or similar functionality that identifies "text-level shorts," which is alleged to constitute generating a specific rule deck. | ¶45; Ex. D, p. 67 | col. 6:15-21 |
| (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits... | The accused processes allegedly perform a validation by running the "short finder" to identify short circuits between different signal sources, power, and ground. A visual in the complaint shows a short detected in a layout. (Compl. Ex. D, p. 69). | ¶45; Ex. D, p. 69 | col. 6:22-26 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether the accused functionality of using a "short finder" filter within a larger EDA tool constitutes "generating a specific rule deck" as required by claim 1(c). The court may need to determine if "generating" requires the creation of a new, standalone data object or if applying a filter to an existing rule set meets the claim's scope.
- Technical Questions: The infringement analysis may turn on the precise definition of "texted metal short circuits between different signal sources in addition to power and ground." The evidence will need to establish that the shorts identified by Micron’s processes fall within the specific technical scope of this claim language.
’803 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method for performing dummy metal insertion in design data for an integrated circuit, which includes dummy metal objects inserted by a dummy fill tool, comprising: | Micron’s accused processes allegedly employ a design tool, such as from Cadence, to perform dummy metal insertion for its SSD controller layouts. | ¶56; Ex. C, p. 39 | col. 5:5-7 |
| (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; | After an ECO, Micron’s accused processes allegedly perform a Design Rule Check (DRC) to determine if there are rule violations, including those caused by dummy fill intersecting with new layout changes. The complaint provides a diagram illustrating this process. (Compl. Ex. C, p. 51). | ¶57; Ex. C, p. 41 | col. 5:8-11 |
| and (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool. | Micron’s accused processes allegedly allow designers to "trim metal fill geometries that cause the short or DRC violation," which is alleged to constitute deleting the intersecting objects without rerunning the full dummy fill tool. A diagram in the complaint shows dummy fill being deleted after a new wiring pattern is added. (Compl. Ex. C, p. 51). | ¶58; Ex. C, p. 43 | col. 5:11-14 |
- Identified Points of Contention:
- Scope Questions: The dispute may focus on the meaning of "deleting." The court will have to decide if the accused functionality of "trimming" or "repairing" a dummy fill object is equivalent to "deleting the intersecting dummy metal objects." A defendant might argue that "deleting" requires removing the entire object, whereas "trimming" only removes a portion.
- Technical Questions: A key question will be whether the accused process performs the claimed steps in the required order. The claim recites first "performing a check" and then "deleting." The evidence will need to show whether the accused tool performs these as distinct logical steps or as a single integrated "repair" function that may not map directly onto the claim language.
V. Key Claim Terms for Construction
'989 Patent: "generating a specific rule deck" (Claim 1)
- Context and Importance: This term is central to the inventive concept of performing a focused, early-stage validation. Infringement hinges on whether Micron's alleged use of a "short finder" tool, which isolates certain rules, meets this "generating" requirement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the invention as "reducing the standard design rule deck used for physical design validation to include only those design rules needed to detect texted metal short circuits" (’989 Patent, col. 4:16-20). This language could support an interpretation where filtering, selecting, or invoking a subset of rules constitutes "generating."
- Evidence for a Narrower Interpretation: The patent’s flowchart (Fig. 3) depicts "GENERATE A SPECIFIC RULE DECK" (308) as a discrete step separate from "RECEIVE AS INPUT A PHYSICAL DESIGN RULE DECK" (306). This could suggest that "generating" requires the creation of a new, persistent, and distinct file or data structure, rather than merely applying a temporary filter during execution.
'803 Patent: "deleting the intersecting dummy metal objects" (Claim 1)
- Context and Importance: The complaint alleges the accused tool "trims" and "repairs" dummy fill violations. (Compl. ¶58). The case may turn on whether this "trimming" action falls within the scope of "deleting."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The purpose of the step is to "avoid[] having to rerun the dummy fill tool." An interpretation where "deleting" includes trimming or removing only the intersecting portion of an object would be consistent with achieving this stated goal.
- Evidence for a Narrower Interpretation: The flowchart in Figure 2 of the patent shows that when an "Intersection" is found, the subsequent step is to "Delete the object" (114). This language could support a narrower reading that requires the removal of the entire dummy metal object that was found to intersect, not just a portion of it. The specification also states, "If an intersecting dummy metal object 18 is found, then in step 132 the dummy metal object 18 is deleted" (’803 Patent, col. 4:46-48).
VI. Other Allegations
- Indirect Infringement: The complaint includes boilerplate allegations of indirect infringement for both patents. (Compl. ¶47, 60). It does not, however, plead specific facts to support the requisite knowledge and intent, such as pre-suit notice or analysis of Defendant's instructional materials.
- Willful Infringement: The complaint does not contain a specific count for willful infringement. It does allege that infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285, but it does not plead facts suggesting pre-suit knowledge of the patents that would typically support a willfulness claim. (Compl. ¶48, 61).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central question for the ’989 patent will be one of process equivalence: Does Micron's alleged use of a "short finder" function within a larger EDA tool constitute the discrete, sequential method of "generating a specific rule deck" and then "performing a physical design validation" using only that deck, as claimed, or is it a fundamentally different, integrated process?
- For the ’803 patent, a core issue will be one of functional scope: Does the accused process of "trimming" or "repairing" a portion of a dummy fill object that causes a design rule violation meet the limitation of "deleting the intersecting dummy metal objects," or does the claim require the removal of the entire object?
- A key evidentiary question across both patents will be how Micron’s EDA tools actually function at a detailed technical level. The outcome may depend on whether the publicly-available documentation cited in the complaint accurately reflects the specific, granular steps performed by the software configurations used internally by Micron.