DCT
1:22-cv-00417
Bell Semiconductor LLC v. Micron Technology Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Micron Technology, Inc. (Idaho)
- Plaintiff’s Counsel: Givens Pursley LLP
- Case Identification: 1:22-cv-00417, D. Idaho, 10/05/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Idaho because Defendant maintains its headquarters and a regular and established place of business in Boise, Idaho, where it employs thousands of individuals, including engineers in design-related roles.
- Core Dispute: Plaintiff alleges that Defendant’s methodologies for designing semiconductor chips infringe a patent related to efficiently implementing engineering changes in an integrated circuit design.
- Technical Context: The technology pertains to electronic design automation (EDA), a field focused on software tools used to design complex integrated circuits, where efficiency improvements can significantly reduce time-to-market.
- Key Procedural History: The complaint's supporting expert declaration notes that during the prosecution of the patent-in-suit, the applicant amended the claims to clarify that the routing process was "incremental" and confined to a specific "window," distinguishing it from prior art that re-processed the entire circuit design. This amendment may be significant for claim construction.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | ’626 Patent Priority Date |
| 2007-06-12 | ’626 Patent Issue Date |
| 2022-10-05 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows
The Invention Explained
- Problem Addressed: The patent's background describes that prior methods for implementing an engineering change order (ECO) in an integrated circuit (IC) design were highly inefficient (Compl. ¶23; ’626 Patent, col. 2:15-19). Design tools had to be run for the entire circuit design, even for a minor change, resulting in a "typical turnaround time" of about one week regardless of the change's size (Compl. ¶24; ’626 Patent, col. 2:37-44).
- The Patented Solution: The invention proposes a method to localize the design work required by an ECO. It involves creating a "window"—a defined area smaller than the entire IC design—that encloses the change (Compl. ¶4). Key design processes, such as routing, are then performed only on the electrical connections ("nets") within that window. The results from this incremental process are then merged into a copy of the original design to create a revised version, avoiding the need to re-process the entire chip (Compl. ¶4; ’626 Patent, Abstract; col. 3:19-23).
- Technical Importance: This method allows the time required to implement an ECO to scale with the size of the change itself, rather than the size of the entire, often massive, integrated circuit, providing significant savings in time and computational resources (Compl. ¶25; ’626 Patent, col. 2:47-53).
Key Claims at a Glance
- The complaint, via its exhibits, asserts infringement of independent claim 1 and dependent claims 2-4 (’626 Patent, col. 7:7-8:25; Compl. Ex. B).
- Independent Claim 1 requires:
- receiving as input an integrated circuit design;
- receiving as input an engineering change order to the integrated circuit design;
- creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design;
- performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window;
- replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and
- generating as output the revised integrated circuit design.
- The complaint reserves the right to assert additional claims (Compl. Ex. B, p. 27).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Processes" as the design methodologies used by Micron to create its semiconductor products, with the design of the "Micron 2200 MTFDHBA256TCK-1AS1AABYY 256GB NVMe PCIe3.0x4 TLC M.2 22x80mm SSD" cited as a specific example (Compl. ¶1, 37).
Functionality and Market Context
- The complaint alleges that Micron utilizes EDA tools from vendors such as Cadence, Synopsys, or Siemens to design its chips (Compl. ¶37). The infringement theory centers on Micron's alleged use of features within these tools that perform incremental design changes. For example, the complaint provides a diagram from a Cadence Innovus user guide illustrating a "Parallel Edit Flow." This visual depicts a process where multiple users can make localized design changes to different areas of a single chip design simultaneously (Compl. Ex. B, p. 29). The complaint alleges these localized design methodologies, which perform processes like routing, design rule checks, and parasitic extraction within defined windows, are used to produce Micron's semiconductor devices (Compl. ¶37-39). The complaint does not provide detail on the specific market context of the accused SSD beyond its product name.
IV. Analysis of Infringement Allegations
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality - | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | The Accused Processes allegedly begin by loading or importing an existing circuit design into an EDA tool. The complaint references a diagram showing a "Design import" step in the Cadence Innovus tool (Compl. Ex. B, p. 30). - | ¶36; Ex. B, p. 30 | col. 6:1-3 |
| (b) receiving as input an engineering change order to the integrated circuit design; | Micron's process allegedly receives an ECO, for example, by using a command like "start_parallel_edit" in the EDA tool to initiate a design change (Compl. Ex. B, p. 31). - | ¶37; Ex. B, p. 31 | col. 6:4-6 |
| (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; | The EDA tool's "start_parallel_edit" command allegedly uses a "-region" parameter with specific coordinates to define a window for the ECO that is smaller than the full chip. A visual in the complaint shows a yellow box labeled "Area 1" overlaid on a portion of a chip layout, representing such a window (Compl. Ex. B, p. 33). - | ¶37; Ex. B, p. 33 | col. 6:7-12 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | The Accused Processes allegedly perform routing and design rule fixes only within the assigned area defined by the window. The complaint points to documentation stating the tool can be restricted to write out only objects inside or touching the specified edit area (Compl. Ex. B, p. 33, 34). - | ¶37; Ex. B, p. 34 | col. 6:13-16 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; | The process allegedly uses a command like "read_parallel_edit_files" to load the files containing the incremental changes (".eco" files) and merge them into the main design, thereby replacing the original data in the windowed area with the revised data (Compl. Ex. B, p. 36). - | ¶37; Ex. B, p. 36 | col. 6:17-21 |
| (f) generating as output the revised integrated circuit design. | The process of loading the incremental changes results in a revised integrated circuit design, which the complaint alleges is then output for subsequent design steps or manufacturing (Compl. Ex. B, p. 36). - | ¶37; Ex. B, p. 36 | col. 6:22-23 |
Identified Points of Contention
- Scope Questions: A central question may be one of attribution and use. The complaint’s evidence focuses heavily on the documented capabilities of third-party EDA tools. The case may turn on what evidence shows that Micron’s actual design processes for its products "use" these tool capabilities in a manner that performs the complete, ordered sequence of steps required by the patent claims.
- Technical Questions: The infringement analysis will likely scrutinize whether the accused EDA tool's functionality maps precisely onto the claim limitations. For example, does the tool's "incremental routing" process operate exclusively on nets within the window as required by the "only for each net... enclosed" language, or does the tool's algorithm consider or affect nets outside the window, potentially creating a mismatch with the claim?
V. Key Claim Terms for Construction
The Term: "window"
- Context and Importance: This term is the central organizing concept of the invention. Its construction will define the boundaries of the claimed incremental process and is therefore critical to the scope of all claims.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification provides a broad definition: "a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 3:59-62). This suggests the term is not tied to any specific method of creation.
- Evidence for a Narrower Interpretation: The detailed description provides specific examples of how windows are created, such as by calculating a "bounding box that includes the port instances for each net changed" or by including "affected nets" that have a coupling capacitance exceeding a certain threshold (’626 Patent, col. 4:36-40; col. 3:65-4:2). A party could argue these specific embodiments should inform or limit the term's meaning.
The Term: "performing an incremental routing... only for each net in the integrated circuit design that is enclosed by the window"
- Context and Importance: This limitation captures the core efficiency gain of the invention. The interpretation of "only for each net" will be a focal point, as it dictates the degree of isolation required for the infringing process. Practitioners may focus on this term because it presents a potential non-infringement argument based on the complex, interdependent nature of routing algorithms.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A broader reading would interpret "only" as distinguishing the claimed method from the prior art, where the routing tool was run "for the entire integrated circuit design" (’626 Patent, col. 2:17-18). Under this view, the key is that the process is directed at the window, not the whole design.
- Evidence for a Narrower Interpretation: A narrower reading would require absolute process isolation. The patent itself notes that if a net is found to be "open" (i.e., not fully contained in the window), it is "frozen" and not changed by the router (’626 Patent, col. 4:11-15). A defendant could argue that if an accused process considers, analyzes, or is influenced by any net data outside the window, it fails to meet the strict "only for" limitation.
VI. Other Allegations
- Indirect Infringement: The complaint makes a conclusory allegation of indirect infringement (Compl. ¶42) but does not plead specific facts to support the elements of knowledge or intent required for induced infringement, nor does it identify any non-staple components for a contributory infringement theory.
- Willful Infringement: The complaint does not explicitly allege willful infringement. It does, however, plead that the infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶43), but it does not allege pre- or post-suit knowledge of the patent to support such a claim.
VII. Analyst’s Conclusion: Key Questions for the Case
- A key evidentiary question will be one of process attribution: what evidence will be required to prove that Micron's actual, internal design workflows for its commercial products perform the specific, ordered sequence of steps in Claim 1, beyond simply showing that it uses third-party EDA tools that possess the alleged capabilities?
- The case will likely involve a central issue of claim scope and functional equivalence: does the accused EDA tool's "incremental" or "parallel edit" functionality operate in a way that is technically indistinct from the patent's requirement of "performing an incremental routing... only for each net... that is enclosed by the window"? The interpretation of this "only" limitation will be critical to the infringement analysis.