1:25-cv-00073
Micron Technology Inc v. Polaris Powered Tech LLC
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Micron Technology, Inc. and Micron Semiconductor Products, Inc. (Delaware/Idaho)
- Defendant: Polaris Powerled Technologies, LLC (California)
- Plaintiff’s Counsel: Holland & Hart LLP; Jones Day
- Case Identification: 1:25-cv-00073, D. Idaho, 02/07/2025
- Venue Allegations: Plaintiff alleges venue is proper in the District of Idaho because Defendant purposefully directed activities at Idaho residents by sending demand letters to Plaintiff’s headquarters in Boise, Idaho.
- Core Dispute: Plaintiff seeks a declaratory judgment that its solid-state drive (SSD) products do not infringe eight patents asserted by Defendant and that several of the asserted patents are unenforceable due to issues of ownership, licensing, and alleged inequitable conduct during prosecution.
- Technical Context: The technology concerns methods for managing data in nonvolatile memory systems, including techniques for handling interrupts, dispatching commands, and performing error correction within memory controllers for SSDs.
- Key Procedural History: The complaint alleges that Defendant is a non-practicing entity engaging in a pattern of bad-faith assertions. Plaintiff claims it is a co-owner of or licensed to three of the asserted patents (’968, ’346, ’228) through a 2009 development agreement with the original patent assignee, Integrated Device Technology (IDT). The complaint also alleges that another asserted patent (’245) is unenforceable because it is subject to a terminal disclaimer with a patent not owned by Defendant. Further, Plaintiff alleges Defendant accused a product (M600 SSD) that was discontinued before one of the asserted patents (’405) was issued and whose last sale falls outside the six-year damages window.
Case Timeline
| Date | Event |
|---|---|
| 2009-07-02 | Micron and IDT enter into Product Development and License Agreement |
| 2010-08-16 | Priority Date for ’968, ’228, and ’346 Patents |
| 2012-05-22 | Priority Date for ’337 and ’085 Patents |
| 2013-06-27 | Priority Date for ’245 Patent |
| 2013-10-08 | U.S. Patent No. 8,554,968 Issues |
| 2013-11-19 | U.S. Patent No. 8,588,228 Issues |
| 2013-12-03 | U.S. Patent No. 8,601,346 Issues |
| 2014-09-03 | Priority Date for ’661 and ’405 Patents |
| 2015-04-28 | U.S. Patent No. 9,021,337 Issues |
| 2015-11-10 | U.S. Patent No. 9,183,085 Issues |
| 2016-04-05 | U.S. Patent No. 9,305,661 Issues |
| 2017-02-01 | Last shipment date of accused M600 SSD product |
| 2017-10-24 | U.S. Patent No. 9,799,405 Issues |
| 2017-11-28 | U.S. Patent No. 9,830,245 Issues |
| 2025-01-17 | Polaris sends demand letters to Micron |
| 2025-01-20 | Polaris sends additional demand letter to Micron |
| 2025-02-07 | Complaint for Declaratory Judgment Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 8,554,968 - “Interrupt Technique for a Nonvolatile Memory Controller”
The Invention Explained
- Problem Addressed: In high-performance memory systems, a host computer typically must dedicate resources to monitor 'completion queues' to determine when a memory controller has finished a task ('968 Patent, col. 1:49-54). This monitoring consumes host processing power and can be inefficient.
- The Patented Solution: The invention proposes a nonvolatile memory controller with a dedicated 'interrupt manager' that offloads the monitoring task from the host. This manager independently determines if a completion queue contains an unprocessed status and, if so, generates and sends an 'interrupt message packet' to the host processing unit, alerting it that a task is complete ('968 Patent, Abstract; col. 2:1-26).
- Technical Importance: This approach can improve overall system performance by freeing the host processor from the routine task of polling memory queues, allowing it to perform other computations.
Key Claims at a Glance
- The complaint asserts noninfringement of independent claim 1 (Compl. ¶55).
- Claim 1 of the ’968 Patent requires:
- A nonvolatile memory controller comprising:
- an interrupt manager configured to:
- generate a completion queue state for indicating the occurrence of a completion queue event;
- generate an interrupt vector state based on the completion queue state;
- determine the completion queue of the host processing unit contains an unprocessed completion status based on the interrupt vector state;
- generate an interrupt message packet for triggering an interrupt in the host processing unit; and
- wherein the completion queue state includes a doorbell update status.
- The complaint does not explicitly reserve the right to assert noninfringement of dependent claims.
U.S. Patent No. 8,588,228 - “Nonvolatile Memory Controller with Host Controller Interface for Retrieving and Dispatching Nonvolatile Memory Commands in a Distributed Manner”
The Invention Explained
- Problem Addressed: The patent describes a system for efficiently managing memory commands to avoid processing bottlenecks in a high-performance memory controller that uses multiple processors ('228 Patent, Abstract).
- The Patented Solution: The invention discloses a host controller interface with functionally distinct modules for fetching and dispatching commands. A 'command fetch module' retrieves commands from the host into one of several 'command assembly buffers.' A separate 'command dispatch module' monitors the buffers, and when a buffer contains a command, it selects an available processor and generates a request packet to route the command to that processor for execution. This architecture allows command retrieval and dispatch to occur independently and in parallel ('228 Patent, Abstract; col. 2:1-24). Figure 9 of the patent illustrates this distributed architecture.
- Technical Importance: This distributed approach to command handling enables a memory controller to scale its performance by efficiently distributing tasks across multiple internal processors, a key requirement for modern enterprise-grade SSDs.
Key Claims at a Glance
- The complaint asserts noninfringement of independent claim 1 (Compl. ¶65).
- Claim 1 of the ’228 Patent requires:
- A nonvolatile memory controller comprising:
- a plurality of processors and a host controller interface that includes a command fetch module, a command dispatch module, and a plurality of command assembly buffers;
- the command fetch module configured to detect and retrieve a command from a host, write it to a selected buffer, and update a submission queue head pointer; and
- the command dispatch module configured to determine a buffer contains a command without receiving the submission queue head pointer and tail pointer from the command fetch module, select a processor, and generate a request packet.
- The complaint does not explicitly reserve the right to assert noninfringement of dependent claims.
U.S. Patent No. 8,601,346 - “System and Method for Generating Parity Data in a Nonvolatile Memory Controller by Using a Distributed Processing Technique”
Technology Synopsis
The patent describes a system for efficiently generating parity data (used for error correction, e.g., in RAID) without needing a large data buffer. It uses multiple command processing units and a parity calculator that generates a parity block "on the fly" as it receives a sequence of data blocks.
Asserted Claims
The complaint asserts noninfringement of independent claim 1 (Compl. ¶75).
Accused Features
The complaint alleges that Micron’s products do not contain the claimed "plurality of command processing units" configured to perform the specific data stripe operation as recited (Compl. ¶76).
U.S. Patent No. 9,021,337 - “Systems and Methods for Adaptively Selecting Among Different Error Correction Coding Schemes in a Flash Drive”
Technology Synopsis
The patent describes a method for managing different error correction code (ECC) schemes, or "gears," in a flash memory device. The method involves deciding whether to switch to a stronger ECC gear for a region of memory based on metrics like the raw bit error rate or the number of decoding iterations required.
Asserted Claims
The complaint asserts noninfringement of independent claim 1 (Compl. ¶85).
Accused Features
The complaint alleges that Micron’s products do not perform the claimed step of "deciding whether or not to select a different gear" based on the specific analytical criteria recited in the claim (Compl. ¶86).
U.S. Patent No. 9,183,085 - “Systems And Methods For Adaptively Selecting From Among A Plurality Of Error Correction Coding Schemes In a Flash Drive For Robustness And Low Latency”
Technology Synopsis
The patent describes another method for adaptively selecting an ECC scheme ("gear"). This method involves determining a bit error rate for a memory region and comparing it to predetermined thresholds to select the appropriate gear, where different gears have different data payload sizes and correction capabilities.
Asserted Claims
The complaint asserts noninfringement of independent claim 1 (Compl. ¶94).
Accused Features
The complaint alleges that Micron’s products do not perform the claimed steps of "comparing the determined bit error rate to one or more predetermined thresholds" and "selecting a gear... based at least partly on the comparisons" as required by the claim (Compl. ¶95).
U.S. Patent No. 9,305,661 - “Nonvolatile Memory System That Uses Programming Time To Reduce Bit Errors”
Technology Synopsis
The patent describes a method to reduce bit errors by identifying "weak" memory cells based on how long they take to program. Once identified, pages containing these weak cells are recorded in a lookup table to prevent subsequent programming operations to those pages.
Asserted Claims
The complaint asserts noninfringement of independent claim 1 (Compl. ¶103).
Accused Features
The complaint alleges that Micron’s products do not perform the claimed steps of identifying weak cells "using programming time" or preventing subsequent programming based on a "weak-page lookup table" (Compl. ¶104).
U.S. Patent No. 9,799,405 - “Nonvolatile Memory System With Read Circuit for Performing Reads Using Threshold Voltage Shift Read Instruction”
Technology Synopsis
The patent describes a method for reducing read latency in a memory controller. It involves storing a table of threshold voltage shift read instructions and using a "usage characteristic" of the memory device to determine when to use these specialized read instructions instead of standard ones.
Asserted Claims
The complaint asserts noninfringement of independent claim 1 (Compl. ¶112).
Accused Features
The complaint alleges that Micron’s products do not perform several of the key method steps, including storing the claimed table and indexing it based on a usage characteristic to perform subsequent reads (Compl. ¶113).
U.S. Patent No. 9,830,245 - “Tracing Events in an Autonomous Event System”
Technology Synopsis
The patent describes a system with an "event subsystem" that allows peripheral devices to communicate and trigger actions among themselves directly, without using a central processing unit (CPU) interrupt. A coupled trace circuit monitors and records these signaling events.
Asserted Claims
The complaint asserts noninfringement of independent claim 1 (Compl. ¶121).
Accused Features
The complaint alleges that Micron’s products do not contain the claimed "event subsystem" that transfers signaling events between peripherals "without the use of a central processing unit (CPU) interrupt or a direct memory access (DMA) controller" (Compl. ¶122).
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are Micron’s solid-state drives (SSDs), including the P310 SSD, T700 SSD, P5 SSD, P5 Plus SSD, 9400 Pro SSD, 3500 SSD, and M600 SSD, as well as "other similar products and devices" (Compl. ¶32).
Functionality and Market Context
The accused products are high-performance data storage devices used in consumer and enterprise computing environments (Compl. ¶1). The allegedly infringing functionalities reside within the nonvolatile memory controllers inside these SSDs. These controllers are responsible for managing all data operations, including interfacing with the host system, executing read/write commands, performing error correction, and managing the health of the flash memory cells (Compl. ¶51, 56, 66). The complaint notes that one of the accused products, the M600 SSD, was discontinued in 2016 with a final shipment date in February 2017 (Compl. ¶8).
No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
U.S. Patent No. 8,554,968 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Non-Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [a-3] determine [sic] the completion queue of the host processing unit contains an unprocessed completion status based on the interrupt vector state | The complaint alleges that the accused products do not contain an interrupt manager configured to make this determination "based on the interrupt vector state" as required by the claim. | ¶56 | col. 18:21-25 |
Identified Points of Contention
- Technical Question: A central evidentiary question will be how Micron's accused controllers determine whether a completion queue has an unprocessed status. The dispute will likely focus on whether the logic and inputs for that determination meet the claim requirement of being "based on the interrupt vector state," as that term is defined by the patent's specification and claims. (Compl. ¶56).
U.S. Patent No. 8,588,228 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Non-Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| [b] the command fetch module configured to detect a nonvolatile memory command... by monitoring a submission queue head pointer and a submission queue tail pointer stored in the nonvolatile memory controller... and update the submission queue head pointer | The complaint alleges that the accused products' command fetch module does not perform this function as required. | ¶66 | col. 20:16-25 |
| [c] the command dispatch module configured to determine the selected command assembly buffer contains the nonvolatile memory command without receiving the submission queue head pointer and the submission queue tail pointer from the command fetch module | The complaint alleges that the accused products do not contain a command dispatch module that operates without receiving these specific pointers from the command fetch module. | ¶66 | col. 20:26-31 |
Identified Points of Contention
- Scope Question: A key issue will be the scope of the negative limitation "without receiving the submission queue head pointer and the submission queue tail pointer from the command fetch module." The court may need to determine what level of informational separation between the fetch and dispatch modules is required to meet this limitation.
- Technical Question: An evidentiary dispute may arise over the precise internal architecture and data flow within Micron's controllers. Specifically, the analysis will turn on what information, if any, is passed between the command fetch and command dispatch components regarding queue pointers and where those pointers are stored and monitored. (Compl. ¶66).
V. Key Claim Terms for Construction
’968 Patent, Claim 1: "based on the interrupt vector state"
Context and Importance
This term is central to the infringement analysis for the ’968 Patent. The outcome may depend on whether the method used by Micron's controllers to assess queue status falls within the scope of this phrase. Practitioners may focus on this term because the complaint's non-infringement allegation rests entirely on this limitation (Compl. ¶56).
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation: The specification states the interrupt manager "generates an interrupt vector state... based on the completion queue states" ('968 Patent, col. 15:22-24). This could suggest that any state information derived from the queue state could qualify.
- Evidence for a Narrower Interpretation: Figure 13 and the accompanying text describe the "Interrupt Vector State" (1125) as comprising specific "Interrupt Event Indicators" (1300), including an "Empty Queue Indicator" (1310), "Aggregate Doorbell Update Status" (1315), and "Aggregate Event Count" (1320) ('968 Patent, col. 12:7-14). An argument could be made that the determination must be based on a state containing these specific elements.
’228 Patent, Claim 1: "without receiving the submission queue head pointer and the submission queue tail pointer from the command fetch module"
Context and Importance
This negative limitation defines a required degree of operational independence between the command fetch and dispatch modules. Whether Micron’s products infringe will depend on how their internal components communicate. The dispute will likely center on whether any information related to the pointers flows from the fetch to the dispatch module, and if so, whether that constitutes "receiving" the pointers.
Intrinsic Evidence for Interpretation
- Evidence for a Broader Interpretation (favoring non-infringement): The claim language is absolute ("without receiving"). This may support an argument that any form of communication regarding the pointers, direct or indirect, from the fetch to the dispatch module would place the device outside the claim scope.
- Evidence for a Narrower Interpretation (favoring infringement): The specification describes the command dispatch module as monitoring the command assembly buffers to identify a stored command ('228 Patent, col. 12:58-63). This could support an argument that the claim only prohibits the direct transfer of the pointer values themselves, while still allowing for other status indicators (e.g., a simple "buffer full" flag) to be communicated between the modules.
VI. Other Allegations
The complaint does not provide sufficient detail for analysis of indirect or willful infringement, as it is a complaint for declaratory judgment of noninfringement. However, the complaint makes extensive allegations of unenforceability for the ’968, ’346, and ’228 patents based on inequitable conduct and unclean hands, alleging that the original assignee, IDT, intentionally failed to name Micron inventors and violated a development agreement during prosecution (Compl. ¶¶137-211).
VII. Analyst’s Conclusion: Key Questions for the Case
- A threshold issue will be one of enforceability and ownership: can Polaris enforce the ’968, ’346, and ’228 patents against Micron if, as alleged, the underlying inventions were co-developed under a license agreement with Micron’s predecessor? Similarly, can the ’245 patent be enforced if it is subject to a terminal disclaimer with a patent that Polaris does not own?
- A central evidentiary question will be one of functional operation: do the accused Micron controllers perform the precise, multi-step processes required by the asserted claims (e.g., making determinations "based on the interrupt vector state" or operating "without receiving" specific pointers), or does discovery reveal a fundamental mismatch in their technical implementation?
- A significant legal question, independent of infringement, will be one of statutory conduct: does Polaris’s pattern of assertions, including accusing long-discontinued products and patents it allegedly cannot enforce, constitute a "bad faith assertion of patent infringement" under the relevant Idaho statute, potentially exposing it to damages and attorneys' fees?