DCT

1:23-cv-02690

Seoul Semiconductor Co Ltd v. Ace Hardware Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:22-cv-00156, E.D. Va., 04/15/2022
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Virginia because Defendant maintains a regular and established place of business in the district, including a large redistribution center in Suffolk, Virginia, and has committed acts of infringement by importing and selling accused products within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s sale and importation of various LED bulbs and lighting products infringes ten patents related to fundamental aspects of LED fabrication, semiconductor structure, and packaging.
  • Technical Context: The lawsuit concerns light-emitting diodes (LEDs), the dominant semiconductor technology for modern lighting, which offers significant advantages in energy efficiency, lifetime, and size over conventional light sources.
  • Key Procedural History: The complaint details a series of over a dozen notice-of-infringement letters sent by Plaintiff to Defendant between April 2019 and September 2021, identifying specific patents-in-suit and accused products. Plaintiff alleges Defendant did not provide a substantive response, which forms the basis for the willfulness allegations.

Case Timeline

Date Event
2005-08-29 U.S. Patent No. 7,397,069 Priority Date
2006-05-18 U.S. Patent No. 7,572,653 Priority Date
2007-12-03 U.S. Patent No. 8,659,050 Priority Date
2008-07-08 U.S. Patent No. 7,397,069 Issues
2008-11-18 U.S. Patent No. 9,147,821 Priority Date
2008-11-18 U.S. Patent No. 10,134,967 Priority Date
2009-03-06 U.S. Patent No. 7,667,225 Priority Date
2009-08-11 U.S. Patent No. 7,572,653 Issues
2010-01-05 U.S. Patent No. 9,716,210 Priority Date
2010-02-23 U.S. Patent No. 7,667,225 Issues
2010-11-26 U.S. Patent No. 8,604,496 Priority Date
2011-09-01 U.S. Patent No. 8,981,410 Priority Date
2013-12-10 U.S. Patent No. 8,604,496 Issues
2013-09-24 U.S. Patent No. 9,269,868 Priority Date
2014-02-25 U.S. Patent No. 8,659,050 Issues
2015-03-17 U.S. Patent No. 8,981,410 Issues
2015-09-29 U.S. Patent No. 9,147,821 Issues
2016-02-23 U.S. Patent No. 9,269,868 Issues
2017-07-25 U.S. Patent No. 9,716,210 Issues
2018-11-20 U.S. Patent No. 10,134,967 Issues
2019-04-05 Plaintiff sends first notice-of-infringement letter
2022-04-15 Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,572,653 - “Method of fabricating light emitting diode”, Issued Aug. 11, 2009

The Invention Explained

  • Problem Addressed: The patent’s background section describes how conventional light-emitting diodes (LEDs) suffer from poor light extraction efficiency because light emitted laterally from the active layer becomes trapped by total internal reflection due to the vertical sidewalls of the semiconductor layers (Compl. Ex. A, ’653 Patent, col. 1:59-col. 2:4).
  • The Patented Solution: The invention proposes a fabrication method where the semiconductor layers are etched to have inclined sidewalls. This is achieved by first forming a photoresist mask with a sloped profile, for example through a reflow process, and then using that mask to etch the underlying semiconductor layers, transferring the inclined shape to the final device structure (Compl. Ex. A, ’653 Patent, col. 2:13-24, Fig. 2).
  • Technical Importance: By creating an inclined exit surface instead of a vertical one, this method reduces total internal reflection and allows more of the generated light to escape the chip, thereby improving the overall light emitting efficiency of the LED (Compl. Ex. A, ’653 Patent, col. 2:34-39).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶ 39).
  • Essential elements of claim 1 include:
    • Preparing a substrate.
    • Forming a lower semiconductor layer, an active layer, and an upper semiconductor layer on the substrate.
    • Forming an etching stop pattern on a portion of the semiconductor layer.
    • Forming a photoresist pattern over the upper semiconductor layer and etching stop pattern such that a sidewall of the photoresist pattern is inclined to an upper surface of the substrate.
    • Sequentially etching the semiconductor layers using the photoresist pattern as an etching mask.
    • Removing the photoresist pattern and the etching stop pattern.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 7,667,225 - “Light emitting device”, Issued Feb. 23, 2010

The Invention Explained

  • Problem Addressed: The patent addresses the problem of crystal defects, such as dislocations, that are inherent in Group-III nitride semiconductor layers. These defects act as non-radiative centers that trap charge carriers (electrons and holes), which significantly reduces the internal quantum efficiency of the LED (Compl. Ex. B, ’225 Patent, col. 1:63-col. 2:2).
  • The Patented Solution: The invention introduces the concept of a "carrier trap portion" within the multi-quantum well (MQW) structure of the LED. This portion is engineered to have a band-gap energy that decreases from its periphery to its center, creating a localized energy well. This structure is designed to intentionally trap carriers and promote efficient radiative recombination, effectively competing with the crystal defects for carriers (Compl. Ex. B, ’225 Patent, Abstract; col. 4:15-27).
  • Technical Importance: This technology provides a way to mitigate the detrimental effects of unavoidable material defects, thereby improving the crystal quality and quantum efficiency of the light-emitting device (Compl. Ex. B, ’225 Patent, col. 2:5-9).

Key Claims at a Glance

  • The complaint asserts independent claim 1 (Compl. ¶ 48).
  • Essential elements of claim 1 include:
    • A substrate.
    • A first semiconductor layer on the substrate.
    • A second semiconductor layer on the first semiconductor layer.
    • A multi-quantum well structure between the first and second semiconductor layers.
    • At least one layer within the multi-quantum well structure comprising at least one carrier trap portion.
    • The carrier trap portion having a band-gap energy decreasing from a periphery of the carrier trap portion to a center of the carrier trap portion.
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent.

U.S. Patent No. 9,269,868 - “Semiconductor light emitting element and method for manufacturing semiconductor light emitting element”, Issued Feb. 23, 2016

  • Technology Synopsis: This patent addresses improving LED efficiency by engineering the p-type semiconductor layer. The invention describes a specific three-layer structure adjacent to the light-emitting unit with defined relative Magnesium (Mg) dopant concentrations: a first layer with a low concentration, a second layer with a higher concentration, and a third layer with an intermediate concentration (Compl. Ex. C, ’868 Patent, Abstract). This graded doping profile is intended to improve carrier injection and overall device performance.
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 54).
  • Accused Features: The GLOBE 91497 LED lighting device is accused of infringement, specifically its p-type semiconductor layer, which allegedly contains the claimed three-layer structure with varying dopant concentrations (Compl. ¶¶ 55-56).

U.S. Patent No. 8,604,496 - “Optical semiconductor device”, Issued Dec. 10, 2013

  • Technology Synopsis: This patent describes an LED structure with a "functional part" that includes a plurality of stacked active layers. The invention specifies that at least two of these active layers must include a "multilayer stacked body" (comprising alternating thick and thin film layers), an n-side barrier layer, a well layer, and a p-side barrier layer arranged in a specific order (Compl. Ex. D, ’496 Patent, Abstract). This complex layered structure is designed to control carrier confinement and recombination to enhance efficiency.
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 60).
  • Accused Features: The FEIT BPST19/LED(K) LED bulb is accused, with the complaint alleging its light-emitting layer structure contains the claimed functional part with multiple active layers that include the specified multilayer stacked body and barrier layers (Compl. ¶¶ 63-66).

U.S. Patent No. 8,659,050 - “Slim LED package”, Issued Feb. 25, 2014

  • Technology Synopsis: This patent relates to the physical packaging of an LED chip. The invention describes a slim package design where one of the lead frames has a "chip mounting recess" formed on its surface. The complaint asserts a related claim that also requires the lead frames to have grooves comprising a plurality of sub-grooves with a triangular cross-section (Compl. ¶ 73; Compl. Ex. E, ’050 Patent, Abstract and claim 1). These features are designed to create a thinner package and improve the mechanical bond between the metal lead frames and the transparent encapsulating resin.
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 69).
  • Accused Features: The GLOBE 91497 LED lighting device is accused of infringing, with allegations that its lead frames include a groove with triangular cross-section sub-grooves covered by a resin (Compl. ¶ 73).

U.S. Patent No. 9,147,821 - “Light emitting device”, Issued Sep. 29, 2015

  • Technology Synopsis: The patent describes an LED package structure with first and second lead frames that each have an upper portion and a lower portion. The key inventive feature is that the upper and lower portions have "different planar shapes from each other," such that the upper portions extend further into the space between the lead frames, creating an "inset sidewall" (Compl. Ex. F, ’821 Patent, claim 1). This structure is intended to improve the mechanical locking of the encapsulating material.
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 77).
  • Accused Features: The ACE A45085010KLED4/ACE LED bulb is accused, with the complaint alleging its lead frames have upper portions that extend further into the intervening space than the lower portions, thereby creating the claimed inset sidewall (Compl. ¶¶ 81-82).

U.S. Patent No. 8,981,410 - “Distributed Bragg reflector for reflecting light of multiple wavelengths from an LED”, Issued Mar. 17, 2015

  • Technology Synopsis: This patent relates to a reflector structure placed on the backside of an LED to redirect downward-traveling light back up, increasing efficiency. The invention describes a Distributed Bragg Reflector (DBR) composed of alternating high- and low-index dielectric layers. The DBR is specifically designed with a first portion having layers of a first and second thickness and a second portion having layers of a third and fourth thickness, allowing it to efficiently reflect light of multiple distinct wavelength ranges, such as blue and yellow light in a white LED (Compl. Ex. G, ’410 Patent, Abstract).
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 86).
  • Accused Features: The GLOBE 91497 LED lighting device is accused of having a DBR comprised of interleaved layers of titanium dioxide and silicon dioxide, with upper and lower layers allegedly having different periodic thicknesses to meet the claim limitations (Compl. ¶¶ 89-90).

U.S. Patent No. 9,716,210 - “Light Emitting Diode and Method of Fabricating the Same”, Issued Jul. 25, 2017

  • Technology Synopsis: This patent describes an LED semiconductor structure designed to improve performance by managing carrier behavior. The invention claims a structure including an active region, and below it, a "superlattice layer" and a "spacer layer." A key feature is the bandgap relationship between these layers, where the spacer layer has a bandgap smaller than the barrier layers of the active region but higher than the bandgap of the quantum well layers (Compl. Ex. H, ’210 Patent, Abstract, claim 1).
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 93).
  • Accused Features: The GLOBE 91497 LED lighting device is accused, with analysis of its epi-structure alleged to show the claimed superlattice and spacer layers below the active region with the required bandgap relationship (Compl. ¶¶ 95-96).

U.S. Patent No. 10,134,967 - “Light Emitting Device”, Issued Nov. 20, 2018

  • Technology Synopsis: This patent describes an LED package with a specific lead frame structure designed to enhance the bond with the encapsulating resin. The invention claims lead frames that each include a "fixing hole" located in their interior portions and an "undercut sidewall that envelopes inner bounds of the fixing hole" (Compl. Ex. I, ’967 Patent, claim 17). This creates a complex geometry for mechanical interlocking.
  • Asserted Claims: Independent claim 17 is asserted (Compl. ¶ 100).
  • Accused Features: The ACE A45085010KLED4/ACE LED bulb is accused of containing lead frames with the claimed fixing hole and an undercut sidewall that forms a "fixing space" (Compl. ¶¶ 103-105).

U.S. Patent No. 7,397,069 - “Semiconductor Device”, Issued Jul. 8, 2008

  • Technology Synopsis: This patent addresses the problem of impurities (e.g., from p-type dopants) diffusing into the light-emitting active layer, which degrades the device's reliability and lifetime. The solution is an "impurity diffusion prevention layer" placed between the active layer and the p-type semiconductor layers. This prevention layer is characterized by having a band gap smaller than the surrounding overflow prevention and semiconductor layers, causing it to trap and accumulate the diffusing impurities (Compl. Ex. J, ’069 Patent, Abstract).
  • Asserted Claims: Independent claim 1 is asserted (Compl. ¶ 109).
  • Accused Features: The ACE A45085010KLED4/ACE LED bulb is accused of infringement, with the complaint alleging that analysis of its semiconductor layers reveals a layer with high indium and low aluminum concentration that functions as the claimed impurity diffusion prevention layer with the required smaller band gap (Compl. ¶ 111).

III. The Accused Instrumentality

Product Identification

The complaint identifies three categories of accused products: the FEIT BPST19/LED(K) LED bulb, the ACE A45085010KLED4/ACE LED bulb, and the GLOBE 91497 LED lighting device (Compl. ¶¶ 8-10). The image of the FEIT bulb shows a vintage-style filament bulb (Compl. ¶ 8), while the ACE bulb is a standard A-type bulb (Compl. ¶ 9) and the GLOBE device is a flat, recessed lighting fixture (Compl. ¶ 10).

Functionality and Market Context

The accused instrumentalities are consumer-grade LED lighting products sold by Defendant Ace Hardware, a major national retailer (Compl. ¶¶ 8-10). The complaint’s allegations are based on reverse engineering of the products, focusing on the microscopic structures of the internal LED chips and the physical construction of the LED packages. For example, the complaint provides scanning electron microscope images of the layered semiconductor structure inside the ACE A45085010KLED4/ACE LED bulb to allege infringement of the ’653 patent’s manufacturing method (Compl. ¶¶ 41-43). Similarly, transmission electron microscope images of the FEIT BPST19/LED(K) LED bulb's internal structure are used to support infringement allegations against the ’225 patent (Compl. ¶ 50).

IV. Analysis of Infringement Allegations

’7,572,653 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
preparing a substrate; The LED chip in the accused ACE bulb is formed on a patterned substrate. ¶42 col. 3:4-6
forming a lower semiconductor layer, an active layer, and an upper semiconductor layer on the substrate; The accused LED chip comprises a lower semiconductor layer, an active layer, and an upper semiconductor layer formed on the substrate. ¶43 col. 3:7-10
forming a photoresist pattern over the upper semiconductor layer and the etching stop pattern such that a sidewall of the photoresist pattern is inclined to an upper surface of the substrate, Upon information and belief, the fabrication method includes forming a photoresist pattern with an inclined sidewall, which is then used as an etching mask. ¶44 col. 3:40-50
sequentially etching the upper semiconductor layer, active layer and lower semiconductor layer using the photoresist pattern as an etching mask, Upon information and belief, the semiconductor layers are sequentially etched using the inclined photoresist pattern, resulting in the final inclined structure of the LED chip. ¶44 col. 3:56-64

’7,667,225 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
a substrate; a first semiconductor layer on the substrate; a second semiconductor layer on the first semiconductor layer; The accused FEIT bulb's LED chip includes a substrate, an n-type semiconductor layer (first layer), and a p-type semiconductor layer (second layer). ¶50 col. 3:45-56
a multi-quantum well structure including at least one well layer and at least one barrier layer between the first semiconductor layer and the second semiconductor layer, The accused LED chip has a multi-quantum well structure between the n-type and p-type layers, comprising brightly colored wells separated by darker barriers. Transmission electron microscope images in the complaint depict this multi-quantum well structure (Compl. ¶ 50). ¶50 col. 3:51-56
at least one layer within the multi-quantum well structure comprising at least one carrier trap portion formed therein, The well layers within the multi-quantum well include indium. ¶51 col. 4:15-18
the at least one carrier trap portion having a band-gap energy decreasing from a periphery of the carrier trap portion to a center of the carrier trap portion. The concentration of indium allegedly varies across the layer, with transitions from high to low concentration corresponding to carrier trap portions and a related drop in band-gap energy. ¶51 col. 4:18-27

Identified Points of Contention

  • Evidentiary Questions for Process Claims: For the ’653 patent, which claims a method of manufacturing, the complaint alleges infringement under 35 U.S.C. § 271(g) by importing a product made by that process. A central issue will be whether the physical characteristics of the final product—specifically, its inclined sidewalls—are sufficient evidence to establish that the specific claimed steps, such as forming an inclined photoresist pattern via a reflow process, were actually performed during manufacturing, which likely occurred overseas.
  • Technical Questions for Structural Claims: For the ’225 patent, the analysis may focus on whether the visual artifacts in the microscope images (e.g., "brightly colored wells" and alleged variations in indium concentration) can be definitively correlated with the functional limitation of a "band-gap energy decreasing from a periphery ... to a center." This raises the evidentiary question of what technical analysis connects the visual data to the claimed energy profile.

V. Key Claim Terms for Construction

For the ’653 Patent

  • The Term: "a sidewall of the photoresist pattern is inclined"
  • Context and Importance: The invention's entire premise for improving light extraction efficiency rests on creating this inclined structure, which is then transferred to the semiconductor layers. The definition of "inclined" will be critical to determining infringement.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The specification suggests a broad range of angles, stating the sidewall may have an "inclined angle in the range of 10~80 degrees with respect to the upper surface of the substrate" (Compl. Ex. A, ’653 Patent, col. 2:30-33). This could support a construction covering any non-vertical orientation within this wide range.
    • Evidence for a Narrower Interpretation: A party might argue the term is limited by the disclosed method of achieving the inclination, specifically "performing a reflow process to the photoresist pattern" (Compl. Ex. A, ’653 Patent, col. 2:25-28). This could raise the question of whether an inclined sidewall formed by a different method would fall outside the claim scope.

For the ’225 Patent

  • The Term: "carrier trap portion"
  • Context and Importance: This appears to be a term of art defined by the patentee to describe the core of the invention. Its construction will determine whether observed indium fluctuations in an accused device meet the claim limitations. Practitioners may focus on this term because it is defined functionally by its effect on band-gap energy.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The patent describes the portion’s function as trapping carriers that would otherwise be lost to dislocations, and states it can be formed by creating an indium concentration gradient (Compl. Ex. B, ’225 Patent, col. 4:15-27). This could support a broad definition covering various forms of indium-rich regions that create a localized energy minimum.
    • Evidence for a Narrower Interpretation: The claim requires the band-gap energy to be "decreasing from a periphery... to a center." The specification further details that this decrease can be a "straight line shape, in a step shape, or in a curved line shape" (Compl. Ex. B, ’225 Patent, col. 2:26-30). This may support a narrower construction that requires a specific, ordered energy gradient rather than just a localized, non-uniform indium concentration.

VI. Other Allegations

Willful Infringement

The complaint alleges willful infringement for all asserted patents. The basis for this allegation is a detailed history of pre-suit notice provided to Defendant Ace Hardware, beginning on April 5, 2019 (Compl. ¶ 25). The complaint alleges that Plaintiff sent numerous letters identifying specific infringing products and patents-in-suit, and that Defendant "did not respond to this letter" or subsequent follow-ups, while allegedly continuing to import and sell the accused products (Compl. ¶¶ 25-37). This alleged pre-suit knowledge and subsequent conduct forms the primary basis for the willfulness claim (Compl. ¶ 46, 58, etc.).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A central issue will be one of evidentiary proof for process infringement: For the ’653 patent, which claims a manufacturing method, can the Plaintiff demonstrate through reverse engineering of the final product that the accused LED chips were necessarily made by the claimed process, including the specific step of forming an inclined photoresist pattern, without direct evidence from the overseas manufacturing facility?
  • A second core issue will be one of functional vs. structural definition: For multiple device patents like the ’225 and ’069, the case may turn on whether the microstructures observed in the accused products meet the patents' functionally-defined limitations. This raises the key question for the court: does the evidence show that observed variations in material composition (e.g., indium concentration) actually perform the claimed functions of creating a "carrier trap portion" with a specific energy gradient or an "impurity diffusion prevention layer" with a specific band gap relationship?
  • Finally, the case presents a broad question of claim scope and industry practice: Given the assertion of ten patents covering diverse aspects of LED design from chip-level semiconductor physics to package-level mechanical structures, a key question will be how the construction of claims across this portfolio aligns with standard, widely adopted technologies in the modern LED lighting industry.