HFT Solutions LLC v. Citadel Securities LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: HFT Solutions, LLC (Delaware)
  • Defendant: Citadel Securities LLC (Delaware)
  • Plaintiff’s Counsel: Russ August & Kabat
• Case Identification: 1:24-cv-13213, N.D. Ill., 12/24/2024
• Venue Allegations: Plaintiff alleges venue is proper in the Northern District of Illinois because Defendant has a principal place of business in Chicago, conducts business in the district, and has committed acts of infringement in the district through its use of the Accused Instrumentalities.
• Core Dispute: Plaintiff alleges that Defendant’s high-frequency trading systems, which utilize Field Programmable Gate Array (FPGA) platforms, infringe three patents related to reducing latency by using an external phase-locked loop to synchronize clock signals.
• Technical Context: The technology concerns specialized hardware architectures for ultra-low latency data processing, which is critical in high-frequency trading where competitive advantages are measured in nanoseconds.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
2018-11-05	Earliest Priority Date for ’286, ’305, and ’381 Patents
2021-02-23	U.S. Patent No. 10,931,286 Issues
2021-02-23	Earliest Date of Alleged Infringement
2021-09-21	U.S. Patent No. 11,128,305 Issues
2023-02-07	U.S. Patent No. 11,575,381 Issues
2024-12-24	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 10,931,286 - “Field programmable gate array with external phase-locked loop” (Issued Feb. 23, 2021)

The Invention Explained

• Problem Addressed: In high-speed FPGAs, synchronizing the clock signals for receiving data and transmitting processed data is a critical challenge. Conventional solutions use on-chip "clock domain crossing" circuits, which inherently add processing delays, or latency. In fields like high-frequency trading, even microsecond or nanosecond delays can be detrimental (Compl. ¶19; ’286 Patent, col. 1:31-55).
• The Patented Solution: The invention claims to solve this problem by moving key components of the clock synchronization mechanism outside of the FPGA chip itself. An external phase control circuit—comprising a phase detector, a controller, and an adjustable oscillator—compares the FPGA's receiver-side clock with its transmitter-side clock. It then adjusts the transmitter's clock source to match the receiver's phase, creating a phase-locked loop (PLL) that operates externally. This architecture is designed to eliminate the need for the latency-inducing internal clock domain crossing circuits (’286 Patent, col. 2:1-3, Fig. 2).
• Technical Importance: This approach suggests a system-level architectural solution to a chip-level problem, trading on-chip integration for potentially lower latency in highly specialized, performance-sensitive applications (’286 Patent, col. 1:46-55).

Key Claims at a Glance

• The complaint asserts independent claim 1 of the ’286 Patent (Compl. ¶23, Count 1).
• Claim 1 is a method claim with the following essential elements:
  • Receiving a first serial data stream and a first clock signal at an FPGA.
  • Generating a first receiver side clock signal within the FPGA based on the first clock signal.
  • Transmitting the receiver side clock signal to a phase detector that is "part of the field programmable gate array system and not part of the field programmable gate array."
  • Generating a feedback clock signal using an external adjustable oscillator, based on input from the phase detector and an external phase controller.
  • Generating a first transmitter side clock signal within the FPGA based on a signal from the adjustable oscillator.
  • Performing computational operations on the data without using clock domain crossing operations that delay processing.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 11,128,305 - “Field programmable gate array with external phase-locked loop” (Issued Sep. 21, 2021)

The Invention Explained

• Problem Addressed: Similar to the ’286 Patent, the ’305 Patent addresses the technical problem of latency introduced by on-chip clock synchronization circuits in FPGAs used for high-speed processing applications (’305 Patent, col. 1:36-52).
• The Patented Solution: The ’305 Patent, which is a continuation of the application that led to the ’286 Patent, describes a system architecture that also uses an external phase control circuit to phase-match the FPGA's internal receiver and transmitter clocks. The system includes an external phase detector that compares the two clock signals and an external adjustable oscillator that adjusts the transmitter-side clock, thereby avoiding the need for an internal clock domain crossing circuit (’305 Patent, Abstract; col. 2:3-67).
• Technical Importance: This patent further develops the system-level architecture for minimizing latency, suggesting its continued relevance in the field of high-performance computing (’305 Patent, col. 1:53-62).

Key Claims at a Glance

• The complaint asserts independent claim 1 of the ’305 Patent (Compl. ¶10, Count 2).
• Claim 1 is a system claim with the following essential components:
  • An FPGA comprising a first interface, a deserializer, computational circuitry, and a serializer.
  • An external phase control circuit, "provided outside of the field programmable gate array," that includes:
    • A phase detector connected to receive clock outputs from the FPGA's deserializer and serializer.
    • A phase controller to determine adjustment information based on the phase detector's output.
    • An adjustable oscillator to generate a clock signal for the FPGA's serializer based on the adjustment information.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 11,575,381 - “Field programmable gate array with external phase-locked loop” (Issued February 7, 2023)

• Technology Synopsis: The ’381 Patent, part of the same patent family, also describes a method and system for reducing latency in FPGAs by using an external phase-locked loop. It addresses the problem of processing delays caused by internal clock domain crossing circuits and proposes synchronizing the receiver and transmitter clocks using an external phase control circuit to achieve phase alignment without such delays (Compl. ¶19, Count 3; ’381 Patent, col. 1:43-65).
• Asserted Claims: The complaint asserts independent claim 1 (Compl. ¶23, Count 3).
• Accused Features: The complaint alleges that Defendant’s use of its high-frequency trading systems, including the specified FPGA boards, infringes the ’381 Patent (Compl. ¶¶7-8, 21, 23, Count 3).

III. The Accused Instrumentality

Product Identification

The Accused Instrumentalities are FPGA-based systems and platforms used by Citadel in its high-frequency trading strategies (Compl. ¶¶6-7). The complaint specifically identifies FPGA boards such as the Bittware XUP-VV8 and AMD Alveo UL3524 and UL3422 (Compl. ¶7).

Functionality and Market Context

The complaint alleges that these FPGA systems are configured and used by Citadel to achieve extremely low-latency trade execution, which is fundamental to the success of high-frequency trading (Compl. ¶¶6, 8). It is alleged that these systems are essential for Citadel's strategies, which rely on executing trades "microseconds or nanoseconds faster, than competitors" (Compl. ¶6). The complaint quotes marketing materials stating these devices deliver "less than 3ns latency for world-class trade execution" (Compl. ¶8).

IV. Analysis of Infringement Allegations

The complaint references, but does not attach, claim chart exhibits that allegedly detail the infringement. The infringement theory is therefore summarized in prose based on the complaint's narrative allegations.

’286 Patent Infringement Allegations

The complaint alleges that Defendant's use of the Accused Instrumentalities directly infringes at least claim 1 of the ’286 Patent (Compl. ¶21, 23, Count 1). The narrative suggests that by configuring and operating its FPGA-based trading platforms, Citadel performs the method steps recited in the claim for processing high-speed data streams with minimal latency. The complaint incorporates by reference an "Exhibit 4" which purportedly provides a detailed mapping of the elements of claim 1 to the functionality of the Accused Instrumentalities (Compl. ¶23, Count 1). This exhibit is presented as visual evidence demonstrating how Citadel's systems satisfy the claim limitations (Compl. ¶23, Count 1).

’305 Patent Infringement Allegations

The complaint alleges that the Accused Instrumentalities directly infringe at least claim 1 of the ’305 Patent because they contain the components of the claimed system (Compl. ¶8, 10, Count 2). The infringement theory is that Citadel’s trading platforms are systems that comprise an FPGA and an external phase control architecture as claimed. The complaint incorporates by reference an "Exhibit 5" as visual evidence that allegedly demonstrates how the Accused Instrumentalities meet the limitations of claim 1 (Compl. ¶10, Count 2).

Identified Points of Contention

• Scope Questions: A central question may be whether the components in Citadel's trading systems that perform clock synchronization qualify as being "outside of the field programmable gate array" or "not part of the field programmable gate array" as required by the claims (’286 Patent, claim 1(h); ’305 Patent, claim 1(b)). The physical and operational relationship between the FPGA boards and other components in Citadel's proprietary trading infrastructure could be a key factual dispute.
• Technical Questions: The complaint alleges Citadel "configures and uses" the FPGA systems (Compl. ¶8). A key question for the court will be what specific configurations Citadel applies and whether those configurations, in operation, meet every limitation of the asserted claims. For the method claims of the ’286 Patent, Plaintiff will need to provide evidence of Citadel performing each claimed step.

V. Key Claim Terms for Construction

Term from the ’286 Patent: "a phase detector that is ... not part of the field programmable gate array"

• Context and Importance: This term is critical because the core inventive concept is the externalization of the phase control loop to avoid on-chip latency. The dispute may center on the physical and functional boundary between the "FPGA" itself and the surrounding "system." Practitioners may focus on this term because the defendant could argue that its control logic is so tightly integrated with the FPGA that it is functionally "part of" the array, even if on a separate physical component.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification consistently depicts the phase detector and controller as logically and physically separate from the FPGA block in diagrams (e.g., ’286 Patent, Fig. 2, item 2206 shown outside block 2100). This may support an interpretation where "not part of" means not physically located on the same integrated circuit as the FPGA core.
  • Evidence for a Narrower Interpretation: The claim uses the term "field programmable gate array system," which is defined to include both the FPGA and the external circuit (’286 Patent, col. 2:4-6). A defendant might argue that if a component is part of the overall "system," the distinction of whether it is "part of" the array itself is ambiguous without a more explicit definition in the specification.

Term from the ’305 Patent: "a phase control circuit, provided outside of the field programmable gate array"

• Context and Importance: Similar to the term from the ’286 Patent, the location of the "phase control circuit" is fundamental to the infringement and validity analysis. The definition of "outside" will likely be a central point of contention.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The Summary of the Invention explicitly states the "phase control circuit" is "provided outside of the field programmable gate array" and lists its components (phase detector, controller, oscillator) (’305 Patent, col. 2:60-62). This language suggests a clear physical separation is intended.
  • Evidence for a Narrower Interpretation: A defendant could argue that "provided outside" is ambiguous in the context of modern, highly integrated systems where multiple components may be co-packaged or reside on the same printed circuit board. They may argue that "outside" requires a greater degree of physical or operational separation than what is present in the accused systems.

VI. Other Allegations

Willful Infringement

The complaint alleges willful infringement for all three patents based on Defendant’s knowledge of the patents acquired "since at least service of this Complaint" (Compl. ¶24, Count 1; ¶11, Count 2; ¶24, Count 3). This is an allegation of post-suit willfulness only.

VII. Analyst’s Conclusion: Key Questions for the Case

1. A core issue will be one of definitional scope: How will the court construe the boundary between the "field programmable gate array" and the external "phase control circuit"? The case may turn on whether the phrase "outside of the field programmable gate array" refers to a component on a separate silicon die, a separate circuit board, or a functionally distinct module, and whether the accused systems meet that definition.
2. A second central issue will be evidentiary: Since the accused instrumentalities are complex, proprietary trading systems, what evidence will emerge in discovery to demonstrate that Citadel's specific configuration and use of these FPGA platforms practice every element of the asserted method and system claims? The allegations currently rely on incorporating by reference exhibits that have not been made public.
3. A final question relates to technical implementation: Do the accused trading systems, which are designed for minimal latency, achieve this goal through the patented external phase-locking architecture, or do they employ an alternative, non-infringing technical solution to manage clock synchronization and latency?