DCT
1:19-cv-11857
Altair Logix LLC v. Seco USA Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: Seco USA Inc. (Massachusetts)
- Plaintiff’s Counsel: Chavous Intellectual Property Law; Direction IP Law
- Case Identification: 1:19-cv-11857, D. Mass., 08/30/2019
- Venue Allegations: Plaintiff alleges venue is proper in the District of Massachusetts because Defendant is a Massachusetts corporation and resides in the district.
- Core Dispute: Plaintiff alleges that Defendant’s single-board computers, which incorporate NXP i.MX 6 series processors, infringe a patent related to dynamically reconfigurable system-on-chip architectures.
- Technical Context: The technology concerns architectures for integrated circuits that aim to provide the performance of fixed-function hardware with the flexibility of programmable devices at a reduced cost.
- Key Procedural History: The complaint alleges that the asserted independent claim, Claim 1 of the patent-in-suit, was an originally filed claim that issued without amendment and was not rejected during prosecution as being anticipated by prior art.
Case Timeline
| Date | Event |
|---|---|
| 1997-02-28 | U.S. Patent No. 6,289,434 Priority Date |
| 2001-09-11 | U.S. Patent No. 6,289,434 Issue Date |
| 2013-01-01 | Accused UDOO QUAD/DUAL Products Launched (Approx. Date) |
| 2019-08-30 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
- Patent Identification: U.S. Patent No. 6,289,434, “Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates,” issued September 11, 2001.
- The Invention Explained:
- Problem Addressed: The patent addresses the trade-offs between high-performance but inflexible "hard-wired" or "fixed-function" integrated circuits and more flexible but lower-performance alternatives like general-purpose microprocessors, DSPs, and FPGAs (Compl. ¶¶13-17; ’434 Patent, col. 1:42-2:39). Fixed-function systems suffer from "temporal redundancy," requiring the implementation of all possible functions on silicon, which increases cost and wastes resources when functions are not in use (Compl. ¶19; ’434 Patent, col. 2:50-57).
- The Patented Solution: The invention proposes an apparatus with multiple, re-usable "media processing units" (MPUs) that can be dynamically reconfigured at run-time. This architecture is designed to adapt to varying input data and processing requirements, thereby removing redundancy, reducing cost, and achieving the performance of fixed-function implementations without their rigidity (Compl. ¶20; ’434 Patent, col. 3:1-11). Figure 3 of the patent illustrates an exemplary system with multiple MPUs connected to on-chip memory and peripheral interfaces (Compl. ¶23).
- Technical Importance: The described approach sought to provide a novel way to implement systems on a chip that could combine the high performance of application-specific circuits with the cost-efficiency and flexibility of programmable solutions (Compl. ¶12; ’434 Patent, col. 2:64-3:1).
- Key Claims at a Glance:
- The complaint asserts direct infringement of Claim 1 of the ’434 Patent (Compl. ¶26).
- Independent Claim 1 requires:
- An addressable memory for storing data and instructions with a plurality of inputs/outputs.
- A plurality of media processing units, each coupled to the memory and comprising:
- a multiplier;
- an arithmetic unit;
- an arithmetic logic unit capable of operating concurrently with the multiplier or the arithmetic unit; and
- a bit manipulation unit capable of operating concurrently with the arithmetic logic unit and at least one of the multiplier or the arithmetic unit.
- Each of the media processing units must be capable of performing an operation simultaneously with other media processing units.
- Each operation must comprise receiving an instruction and data from memory, processing the data to produce a result, and providing the result to the media processor input/output.
III. The Accused Instrumentality
- Product Identification: The UDOO QUAD and UDOO DUAL single-board computers ("Accused Instrumentality") (Compl. ¶26).
- Functionality and Market Context:
- The Accused Instrumentality is described as an open-source, Arduino-powered mini PC based on the NXP i.MX 6 series of application processors, which feature either dual or quad ARM Cortex-A9 CPU cores (Compl. ¶27, p. 10).
- The complaint alleges that the plurality of ARM Cortex-A9 processors in the i.MX 6 processor function as the claimed "plurality of media processing units" (Compl. ¶28). Each ARM Cortex-A9 core is alleged to contain a NEON media coprocessor, which in turn comprises the functional units (multiplier, arithmetic unit, ALU, bit manipulation unit) recited in the claims (Compl. ¶¶29-32). The "i.MX 6Quad Multimedia Applications Processor Block Diagram" from an NXP datasheet is included in the complaint to show the multiple ARM Cortex-A9 cores, each with an associated NEON unit (Compl. ¶33, p. 23).
- The Accused Instrumentality was launched on Kickstarter in 2013 and is marketed for educational applications and to the "maker" community (Compl. p. 10).
IV. Analysis of Infringement Allegations
’434 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| An apparatus for processing data, comprising: an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs... | The Accused Instrumentality's memory system is alleged to be an addressable memory coupled to the multicore ARM processors through multiple inputs/outputs. A product screenshot describes a memory of "RAM DDR3 1GB" (Compl. pp. 10-11). | ¶27 | col. 55:21-27 |
| a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs... | The multiple ARM Cortex-A9 processors within the NXP i.MX 6 processor are alleged to be the plurality of media processing units. A block diagram in the complaint identifies these as "Media Processors" (Compl. p. 13). | ¶28 | col. 55:28-30 |
| a multiplier having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output | Each processor's NEON media coprocessor is alleged to comprise a multiplier (e.g., an Integer MUL or FP MUL). A diagram of the NEON subsystem is provided, showing an "Integer MUL" and "FP MUL" block (Compl. p. 16). | ¶29 | col. 55:31-35 |
| an arithmetic unit having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output coupled to the media processing unit input/output | Each processor's NEON media coprocessor is alleged to comprise an arithmetic unit (e.g., an FP ADD). The same NEON subsystem diagram is referenced, showing an "FP ADD" block (Compl. p. 20). | ¶30 | col. 55:36-40 |
| an arithmetic logic unit... capable of operating concurrently with at least one selected from the multiplier and arithmetic unit | Each processor's NEON media coprocessor is alleged to comprise an arithmetic logical unit (e.g., an Integer ALU) capable of the claimed concurrent operation. The NEON subsystem diagram shows an "Integer ALU" block (Compl. p. 21). | ¶31 | col. 55:41-47 |
| a bit manipulation unit... capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit | Each processor's NEON media coprocessor is alleged to comprise a bit manipulation unit (e.g., an Integer Shift unit) capable of the claimed concurrent operation. The NEON subsystem diagram shows an "Integer Shift" block (Compl. p. 22). | ¶32 | col. 55:48-55 |
| each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units... | The multiple ARM Cortex-A9 processors on the same chip are alleged to perform operations simultaneously. The complaint provides a block diagram showing the "Quad ARM® Cortex™-A9 Core" configuration (Compl. p. 23). | ¶33 | col. 56:21-24 |
| each operation comprising: receiving at the media processor input/output an instruction... data from the memory, and processing the data responsive to the instruction... and providing... the at least one result at the media processor input/output. | Each ARM Cortex-A9 media processor is alleged to comprise a NEON media coprocessor that receives instructions and data from memory, processes the data to produce a result, and provides the result to the processor input/output (Compl. pp. 25-26). | ¶¶34-35 | col. 56:26-33 |
- Identified Points of Contention:
- Scope Questions: A central question is whether a standard, general-purpose CPU core (ARM Cortex-A9) with an integrated SIMD (Single Instruction, Multiple Data) coprocessor (NEON) falls within the scope of a "media processing unit." The patent repeatedly describes the invention in terms of "adaptively dynamically reconfiguring" computational elements to reduce hardware redundancy (Compl. ¶21; ’434 Patent, col. 3:6-8), a concept that may be argued to be architecturally distinct from a general-purpose processor's fixed pipeline.
- Technical Questions: The complaint alleges that the various functional units (multiplier, ALU, etc.) within the NEON coprocessor operate with the specific concurrency required by Claim 1 (Compl. ¶¶31-32). A key technical question will be whether the evidence cited, primarily high-level block diagrams, is sufficient to demonstrate these specific, fine-grained concurrent operations as claimed, or if the actual hardware pipeline of the Cortex-A9 and NEON unit operates differently.
V. Key Claim Terms for Construction
The Term: "media processing unit"
Context and Importance: This term defines the fundamental building block of the claimed apparatus. The outcome of the infringement analysis may depend heavily on whether the accused ARM Cortex-A9 cores are construed to be "media processing units."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent abstract describes processors that "perform arithmetic-type functions, logic functions and bit manipulation functions," and the specification refers to the MPU as an "aggregate of the dynamically reconfigurable computational and storage elements" (Compl. ¶21). This language could support a construction that reads on any processing unit containing these functional capabilities.
- Evidence for a Narrower Interpretation: The specification's background and summary sections repeatedly emphasize the invention's purpose is to solve the problem of "temporal redundancy" in fixed-function circuits by "adaptively dynamically reconfiguring groups of computational and storage elements in run-time" (’434 Patent, col. 3:14-16). This could support a narrower construction requiring a specific reconfigurable architecture that is distinct from a conventional, fixed-pipeline CPU core.
The Term: "arithmetic unit"
Context and Importance: Claim 1 separately recites a "multiplier", an "arithmetic unit", and an "arithmetic logic unit". The complaint maps these to an "FP MUL," an "FP ADD," and an "Integer ALU" within the NEON coprocessor (Compl. ¶¶29-31). The distinctness of the "arithmetic unit" from the other two components will be a likely point of contention.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent specification, as cited in the complaint, provides an "adder" as an example of an arithmetic element within the Multiplier Accumulator Unit (MAU) (’434 Patent, col. 16:27-61; Compl. ¶22). This could support reading the term on any component that performs addition, such as the accused "FP ADD" block.
- Evidence for a Narrower Interpretation: The claim's recitation of three distinct elements ("multiplier", "arithmetic unit", "arithmetic logic unit") implies they are structurally and functionally distinct. A party could argue that mapping both the "multiplier" and "arithmetic unit" to different operations within a single, highly integrated SIMD pipeline (the NEON coprocessor) does not satisfy the claim's requirement for separate components as understood in the context of the patent's overall architecture.
VI. Other Allegations
The complaint does not contain counts for indirect or willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the term "media processing unit", which is described in the patent in the context of a dynamically reconfigurable architecture designed to eliminate hardware redundancy, be construed to cover a standard, general-purpose ARM Cortex-A9 processor core?
- A key evidentiary question will be one of architectural mapping: do the high-level marketing and technical diagrams cited in the complaint provide sufficient evidence to prove that the internal components of the accused NEON coprocessor (e.g., multiplier, ALU, bit manipulation unit) are distinct units that operate with the specific concurrency required by the limitations of Claim 1, or is there a functional mismatch between the claim language and the actual operation of the accused processor?