DCT
1:22-cv-11386
Bell Semiconductor LLC v. MACOM Technology Solutions Holdings Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: MACOM Technology Solutions, Inc. (Massachusetts)
- Plaintiff’s Counsel: McKool Smith, P.C.; Arrowood LLP; Devlin Law Firm LLC
- Case Identification: 1:22-cv-11386, D. Mass., 11/04/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Massachusetts because Defendant is headquartered there, maintains multiple regular and established places of business, employs a significant number of engineers, and conducts relevant research, development, and manufacturing activities within the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal processes for designing semiconductor chips infringe patents related to methods for verifying circuit designs and for inserting "dummy metal" to aid in manufacturing.
- Technical Context: The patents relate to electronic design automation (EDA), a field of software tools used to design complex integrated circuits, where efficiency and error-checking are critical to managing multi-million dollar development cycles.
- Key Procedural History: The complaint notes that the asserted patents originated from LSI Corporation and are part of a larger portfolio developed by Bell Labs and its successors, but it does not mention any prior litigation, IPR proceedings, or licensing history relevant to the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2003-10-10 | '803 Patent Priority Date |
| 2004-09-22 | '989 Patent Priority Date |
| 2006-12-12 | U.S. Patent 7,149,989 Issues |
| 2007-08-21 | U.S. Patent 7,260,803 Issues |
| 2022-11-04 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,149,989 - “Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design,” issued December 12, 2006
The Invention Explained
- Problem Addressed: In conventional semiconductor design, physical validation is performed at the end of the design cycle. Discovering a fault, such as a short circuit, at this late stage can force a costly reset of the entire design schedule, potentially causing months of delay (Compl. ¶26; ’989 Patent, col. 2:40-46). Conversely, running a full validation check early in the process on an incomplete design generates a large number of false errors, making it difficult to identify genuine problems (Compl. ¶26; ’989 Patent, col. 2:54-58).
- The Patented Solution: The invention proposes a method for performing targeted validation early in the design flow. It generates and uses a "specific rule deck" that is a subset of the full validation rules. This focused rule deck is designed to check only for specific problems, such as "texted metal short circuits," which can be accurately identified in an incomplete design without generating false positives (Compl. ¶27; ’989 Patent, col. 2:64-3:11). This allows designers to catch critical errors early, reducing processing time and turnaround time (Compl. ¶27).
- Technical Importance: The method provides a way to de-risk the complex chip design process by enabling early and accurate detection of a critical class of manufacturing defects, thereby saving significant time and resources. (Compl. ¶8).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶28).
- Claim 1 requires a method with the following essential elements:
- Receiving as input a representation of an integrated circuit design.
- Receiving as input a physical design rule deck that specifies rule checks.
- Generating a "specific rule deck" from the physical design rule deck, where the specific deck includes only rules for "texted metal short circuits between different signal sources in addition to power and ground."
- Performing a physical design validation on the circuit design using the "specific rule deck" to identify those short circuits.
- The complaint does not explicitly reserve the right to assert dependent claims but references infringement of "one or more claims" (Compl. ¶44).
U.S. Patent No. 7,260,803 - “Incremental Dummy Metal Insertions,” issued August 21, 2007
The Invention Explained
- Problem Addressed: Semiconductor manufacturing uses Chemical Mechanical Planarization (CMP) to create smooth, flat layers. This process requires a uniform density of material across the chip's surface. To achieve this, "dummy fill" (non-functional metal) is added to sparse areas (Compl. ¶2). A time-consuming software tool generates this dummy fill pattern. If a customer requests a late-stage design change (an Engineering Change Order, or ECO), the entire dummy fill pattern must be discarded and the tool must be rerun from scratch, a process that can take 30 hours or more and delay the project (Compl. ¶3, ¶35; ’803 Patent, col. 1:51-65).
- The Patented Solution: The invention provides an incremental method to update dummy fill after a design change. Instead of starting over, the process checks to see if any of the new or modified design objects "intersect" with the existing dummy metal objects. If an intersection is found, only the specific intersecting dummy metal objects are deleted, leaving the rest of the valid dummy fill intact. This avoids the need to completely rerun the time-consuming dummy fill tool (Compl. ¶4, ¶36; ’803 Patent, col. 2:5-14).
- Technical Importance: This invention significantly improves design cycle efficiency by transforming a slow, brute-force update process into a fast, targeted, and incremental one, saving significant time and cost when implementing late-stage changes. (Compl. ¶5).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶37).
- Claim 1 requires a method for performing dummy metal insertion that includes dummy metal objects inserted by a dummy fill tool, comprising:
- After a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data.
- Deleting the intersecting dummy metal objects from the design data, "thereby avoiding having to rerun the dummy fill tool."
- The complaint does not explicitly reserve the right to assert dependent claims but references infringement of "one or more claims" (Compl. ¶57).
III. The Accused Instrumentality
Product Identification
- The "Accused Processes" are Defendant MACOM’s internal methodologies for designing and validating semiconductor devices, such as its MAXP-37161B chip (Compl. ¶1, ¶44, ¶57).
Functionality and Market Context
- The complaint alleges that MACOM uses a variety of commercial electronic design automation (EDA) tools from vendors like Cadence, Synopsys, and/or Siemens to implement its design and validation workflows (Compl. ¶45, ¶58). These processes are used to create MACOM's semiconductor products. The specific accused functionality includes using these tools to validate circuit designs for short circuits and to manage the insertion and deletion of dummy metal fill in response to design changes (Compl. ¶47, ¶59-60).
IV. Analysis of Infringement Allegations
’989 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input a representation of an integrated circuit design; | MACOM imports a circuit design for its MAXP-37161B product into one of its EDA design tools. | ¶45 | col. 7:9-11 |
| (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; | MACOM's EDA tools receive various in-design verification processes for concurrent physical design and verification. | ¶46 | col. 7:12-15 |
| (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits...; | MACOM uses an EDA tool that includes a "short finder," "short locator," or similar functionality that identifies texted metal short circuits between different signal nets, including power and ground. | ¶47 | col. 7:16-22 |
| (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits... | The "short finder" or "short locator" functionality is used on the design to identify the short circuits. | ¶47 | col. 7:23-29 |
- Identified Points of Contention:
- Scope Questions: A central question may be whether invoking a "short finder" or "short locator" function within a commercial EDA tool constitutes "generating a specific rule deck" as required by claim 1(c). The court may need to determine if this action is equivalent to creating a subset of rules from a larger deck, or if it is a distinct, pre-programmed operation that falls outside the claim's scope.
- Technical Questions: The analysis may focus on what the term "texted metal short circuits" means in the context of the patent. The case may require evidence on whether the shorts identified by MACOM's tools are specifically "texted" as understood by one of ordinary skill in the art at the time of the invention.
’803 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; | After receiving an Engineering Change Order (ECO), MACOM employs an EDA tool to perform a Design Rule Check (DRC) to find rule violations, including those related to dummy fill geometries intersecting with other design objects. | ¶59 | col. 6:7-11 |
| (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool. | MACOM uses an EDA tool that "repairs DRC violations associated with shorts caused by dummy fill geometries intersecting with other objects" and allows designers to "trim metal fill geometries that cause the short or DRC violation." This is alleged to avoid rerunning the full dummy fill tool. | ¶60 | col. 6:12-14 |
- Identified Points of Contention:
- Scope Questions: The infringement analysis will likely turn on the functional language "thereby avoiding having to rerun the dummy fill tool." A key dispute may be whether the accused process—which "repairs DRC violations" and "trims metal fill"—is the same as the claimed incremental deletion, or if it is a different, more generalized clean-up operation that functionally equates to a rerun, even if it is automated and fast.
- Technical Questions: Evidence will be needed to show that MACOM's process, in response to an ECO, first performs a check for intersections involving pre-existing dummy fill and then selectively deletes only those intersecting objects, as opposed to a process that removes and regenerates all fill in a localized area.
No probative visual evidence provided in complaint.
V. Key Claim Terms for Construction
For the ’989 Patent:
- The Term: "generating a specific rule deck from the physical design rule deck"
- Context and Importance: This term is central because the complaint alleges that using a "short finder" function in a standard EDA tool meets this limitation (Compl. ¶47). The viability of the infringement claim depends on whether this common tool function can be construed as the claimed act of creating a specific, subset rule deck.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification suggests the specific rule deck can be a "separate rule deck" or a "combination of... separate rule decks," and can be "generated directly... in Standard Verification Rule Format (SVRF)" ('989 Patent, col. 5:12-21). This may support an argument that any method of isolating and applying only the relevant rules, regardless of the user interface mechanism, meets the limitation.
- Evidence for a Narrower Interpretation: The flowchart in Figure 3 explicitly depicts "GENERATE A SPECIFIC RULE DECK FROM THE PHYSICAL DESIGN RULE DECK" as a distinct step (308) separate from receiving the original deck (306) and performing the check (310). This could support a narrower construction requiring a discrete act of creating a new, smaller rule file or object, rather than just invoking a mode in a tool.
For the ’803 Patent:
- The Term: "deleting the intersecting dummy metal objects... thereby avoiding having to rerun the dummy fill tool"
- Context and Importance: This is a negative functional limitation that defines the invention's core benefit. The infringement case hinges on proving that MACOM's accused process achieves this result (Compl. ¶60). Practitioners may focus on whether "avoiding having to rerun" means no new dummy fill is calculated at all, or simply that a full, layer-wide recalculation is avoided.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The background section frames the problem as the entire "results of the dummy fill tool are thrown out, and the dummy fill tool is rerun" ('803 Patent, col. 1:56-59). This suggests that any process that preserves the non-intersecting majority of the original dummy fill would meet the "avoiding" limitation, even if some localized re-filling occurs.
- Evidence for a Narrower Interpretation: Claim 1 recites only "deleting the intersecting dummy metal objects," with no mention of adding new ones. The description of the invention also focuses on deleting and then reloading the preserved objects ('803 Patent, col. 4:50-53). This could support a narrow reading that the claimed method is purely subtractive and does not encompass processes that might also perform localized re-filling or repair.
VI. Other Allegations
- Indirect Infringement: The complaint focuses on direct infringement under 35 U.S.C. § 271(a) by MACOM for its use of the accused processes (Compl. ¶44, ¶57). It does not contain specific allegations of inducement or contributory infringement.
- Willful Infringement: The complaint alleges that MACOM's infringement is "exceptional" and requests attorneys' fees under 35 U.S.C. § 285 (Compl. ¶50, ¶63). While the term "willful" is not used, a finding of exceptionality often involves similar conduct. The complaint alleges that MACOM's infringement continued "during the pendency" of the patents, which could be used to argue post-issuance knowledge (Compl. ¶48, ¶61).
VII. Analyst’s Conclusion: Key Questions for the Case
This case appears to center on whether the standard functionalities of commercial EDA software, when used by MACOM, fall within the specific boundaries of the patent claims. The key questions for the court will likely be:
A definitional and functional question for the '989 patent: Can the act of using a built-in "short finder" in a commercial EDA tool be legally and technically equated with the claim requirement of "generating a specific rule deck" from a broader physical design rule deck? Or is it a fundamentally different operation?
An evidentiary and functional question for the '803 patent: Does MACOM's process for handling design changes operate by only "deleting the intersecting dummy metal objects" to preserve the original fill pattern, as claimed, or does its "repair" and "trim" functionality constitute a more generalized local re-filling process that is technically distinct from the patented method?
A question of proof across both patents: Can Bell Semiconductor demonstrate that MACOM's use of off-the-shelf design tools is configured or directed in a way that performs the specific, multi-step methods recited in the claims, rather than merely achieving a similar outcome through the tools' generic, default operations?