DCT
1:22-cv-11698
Bell Semiconductor LLC v. Infineon Tech Americas Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Infineon Technologies America Corp. (California)
- Plaintiff’s Counsel: ARROWOOD LLP; DEVLIN LAW FIRM LLC; MCKOOL SMITH, P.C.
- Case Identification: 1:22-cv-11698, D. Mass., 10/05/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Massachusetts because Defendant maintains a regular and established place of business in the district, including research, development, and manufacturing facilities, and employs numerous engineers there.
- Core Dispute: Plaintiff alleges that Defendant’s process for designing semiconductor chips infringes a patent related to methods for efficiently implementing engineering change orders in integrated circuit designs.
- Technical Context: The technology at issue falls within the field of electronic design automation (EDA), where software tools are used to manage the immense complexity of modern semiconductor design and fabrication.
- Key Procedural History: The complaint notes that the patent-in-suit is part of a larger portfolio originating from companies including Bell Labs, Lucent Technologies, and LSI Corporation. It also references, but does not include, an infringement claim chart and a supporting declaration from a technical expert.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | '626 Patent Priority Date |
| 2007-06-12 | '626 Patent Issue Date |
| 2022-10-05 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
- Patent Identification: U.S. Patent No. 7,231,626, “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows,” issued June 12, 2007. (’626 Patent, front page).
The Invention Explained
- Problem Addressed: The patent’s background section describes prior art methods for implementing engineering change orders (ECOs) in integrated circuit (IC) design as inefficient because they required design tools to be run for the entire circuit, even for minor modifications, resulting in a "typical turnaround time" of "about one week." (’626 Patent, col. 2:15-19, 2:37-41; Compl. ¶24).
- The Patented Solution: The invention claims to solve this problem by creating a "window" that encloses only the portion of the IC design affected by the ECO. Subsequent processing steps, such as routing, are then performed only within this localized window. The results from the window are then merged back into a copy of the overall design to create a revised version, thereby avoiding the need to re-run processes on the entire chip. (’626 Patent, Abstract; col. 3:25-43). Figure 4 of the patent illustrates this concept, showing a smaller window (404) defined within the larger circuit design (402). (’626 Patent, Fig. 4).
- Technical Importance: This method is asserted to provide "significant savings in the resources required to perform routing, design rule check verification, net delay calculation, and parasitic extraction," which shortens the overall design timeline. (’626 Patent, col. 3:18-23; Compl. ¶26).
Key Claims at a Glance
- The complaint asserts infringement of independent method Claim 1. (Compl. ¶30).
- The essential elements of Claim 1 include:
- (a) receiving as input an integrated circuit design;
- (b) receiving as input an engineering change order;
- (c) creating a "window" that encloses the change and is smaller than the entire design area;
- (d) performing "incremental routing" only for nets enclosed by the window;
- (e) replacing the windowed area in a copy of the design with the results of the incremental routing; and
- (f) generating the revised design as output.
- The complaint alleges infringement of "one or more claims" of the patent, suggesting a reservation of rights to assert other claims, including dependent claims. (Compl. ¶37).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Processes" as the design methodologies used by Infineon to create its semiconductor devices, including at least the "Infineon AURIX TC277T64F200SCA Microcontroller." (Compl. ¶¶1, 38).
Functionality and Market Context
- The complaint alleges, on information and belief, that Infineon uses third-party EDA tools from vendors such as Cadence, Synopsys, or Siemens. (Compl. ¶38). The accused functionality is the alleged use of these tools to "perform incremental routing" by "only routing the nets affected by the ECO" and merging the results back into the overall layout. (Compl. ¶38). The complaint further alleges these processes perform localized parasitic extraction and design rule checks only on the nets within the changed area. (Compl. ¶¶39-40). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint references an infringement analysis in an external exhibit which was not provided with the complaint. (Compl. ¶41). The following summary is based on the narrative allegations in the body of the complaint.
'626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | Infineon's Accused Processes allegedly employ design tools that receive an IC design as input to implement an ECO. | ¶38 | col. 6:56-57 |
| (b) receiving as input an engineering change order to the integrated circuit design; | Infineon's Accused Processes are used to implement an ECO. | ¶38 | col. 6:58-60 |
| (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area... | The Accused Processes allegedly perform operations like parasitic extraction and design rule checks "only for each net in the IC design enclosed by the window defining the ECO." | ¶39, ¶40 | col. 6:61-65 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | Infineon's processes are alleged to "perform a method for only routing the nets affected by the ECO." | ¶38 | col. 7:12-15 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing... | The complaint alleges the Accused Processes involve "merging that changed area into the overall circuit layout." | ¶38 | col. 7:1-5 |
| (f) generating as output the revised integrated circuit design. | The Accused Processes are allegedly used "to generate a revised integrated circuit design." | ¶38 | col. 7:6-8 |
- Identified Points of Contention:
- Technical Question: The complaint alleges, on "information and belief," that Infineon's use of general-purpose EDA tools from third-party vendors infringes the patent. (Compl. ¶38). A central question will be what evidence Plaintiff can obtain through discovery to demonstrate how Infineon specifically configures and operates these tools to perform the particular sequence of steps required by the asserted claims.
- Scope Question: Claim 1 requires "creating at least one window...bounded by coordinates." The complaint alleges infringement by describing a process that functionally isolates "nets affected by the ECO." (Compl. ¶38). This raises the question of whether a process that limits operations to a subset of nets meets the claim limitation of "creating" a "window" with defined "coordinates."
V. Key Claim Terms for Construction
The Term: "window"
Context and Importance: The concept of a "window" is fundamental to the patent's purported advance over the prior art, as it enables the localization of design tasks. The outcome of the infringement analysis may depend on whether Infineon's alleged practice of isolating "affected nets" is legally equivalent to "creating" a "window." Practitioners may focus on this term because the complaint's allegations are framed functionally (e.g., "only routing the nets affected") rather than structurally.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification defines a "window" broadly as a "rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area." (’626 Patent, col. 3:59-62). This language might support an interpretation that any method that logically isolates a sub-region for processing falls within the term's scope.
- Evidence for a Narrower Interpretation: Claim 1 explicitly requires that the "window is bounded by coordinates that define an area." (’626 Patent, col. 6:63-65). This language, along with Figure 4 which depicts a discrete, bounded box, could support a narrower construction requiring the definition of a specific geometric area as a predicate step, rather than just a logical grouping of circuit elements.
The Term: "incremental routing"
Context and Importance: This term defines the primary operation performed within the "window." The dispute may involve whether the specific type of routing allegedly performed by Infineon's tools meets the definition of "incremental routing" as understood in the context of the patent.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent repeatedly contrasts its method with processes that operate on the "entire integrated circuit design." (’626 Patent, col. 2:15-19). This could support a reading where any routing process that is not global and operates on a smaller, defined portion of the design qualifies as "incremental."
- Evidence for a Narrower Interpretation: The specification describes streaming windows to an "incremental router" where "only the nets that are modified...are routed." (’626 Patent, col. 4:5-9). An argument could be made that this refers to a specific class of routing algorithms or tools known at the time of the invention, which may have operational characteristics beyond simply being non-global.
VI. Other Allegations
- Indirect Infringement: The complaint includes a conclusory allegation of direct or indirect infringement but does not plead specific facts to support a claim of induced or contributory infringement, such as knowledge or intent to cause infringing acts by others. (Compl. ¶43).
- Willful Infringement: The complaint does not contain an explicit count for willful infringement and does not allege pre-suit knowledge of the ’626 patent. It requests attorneys' fees under 35 U.S.C. § 285 on the basis that the infringement is "exceptional" but provides no specific factual allegations to support that conclusion. (Compl. ¶44).
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of evidentiary proof: The complaint is based on "information and belief" regarding Infineon's internal design processes and use of third-party software. The case will likely depend on whether discovery uncovers direct evidence that Infineon's actual design methodology, and its specific configuration of EDA tools, performs the precise, ordered steps of the asserted claims.
- A second core issue will be one of definitional scope: The case may turn on claim construction, specifically whether the term "creating at least one window... bounded by coordinates" requires the explicit definition of a geometric area as a distinct step, or if it can be read on a process that functionally limits subsequent operations to only those circuit elements affected by a design change.