DCT
1:22-cv-11788
Bell Semiconductor LLC v. MACOM Technology Solutions Inc
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: MACOM Technology Solutions, Inc. (Massachusetts)
- Plaintiff’s Counsel: ARROWOOD LLP; DEVLIN LAW FIRM LLC; MCKOOL SMITH, P.C.
- Case Identification: 1:22-cv-11788, D. Mass., 10/19/2022
- Venue Allegations: Venue is alleged to be proper in the District of Massachusetts because Defendant MACOM maintains its corporate headquarters, additional offices, and research, development, and manufacturing facilities within the district, constituting a regular and established place of business where acts of infringement allegedly occur.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor design processes infringe two patents related to Electronic Design Automation (EDA): one covering methods for efficiently implementing engineering changes in a circuit design, and another for achieving uniform surface density during fabrication by adding "dummy fill" material.
- Technical Context: The lawsuit concerns EDA methodologies, which are foundational software-based processes used to design and verify complex integrated circuits before their costly physical fabrication.
- Key Procedural History: The complaint does not mention any prior litigation, inter partes review (IPR) proceedings, or specific licensing history concerning the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2000-01-18 | ’807 Patent Priority Date |
| 2002-08-20 | ’807 Patent Issue Date |
| 2004-12-17 | ’626 Patent Priority Date |
| 2007-06-12 | ’626 Patent Issue Date |
| 2022-10-19 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows, Issued June 12, 2007
The Invention Explained
- Problem Addressed: The patent’s background section describes prior art methods for implementing an engineering change order (ECO) in an integrated circuit (IC) design as inefficient and time-consuming. Because design tools for routing, validation, and timing analysis operated on the entire IC design, even a small change could require a "typical turnaround time" of about one week, as the entire design had to be re-processed (Compl. ¶¶ 28-29; ’626 Patent, col. 2:15-22, 2:37-44).
- The Patented Solution: The invention proposes a method to significantly reduce this turnaround time by isolating the design change. The solution involves creating a "window"—a defined area smaller than the entire circuit—that encloses the ECO. Subsequent processing steps, like routing, are performed incrementally and only on the circuit nets contained within this window. The results from the window are then merged back into a copy of the original design to create the final revised IC (Compl. ¶4; ’626 Patent, col. 3:19-23, FIG. 6).
- Technical Importance: This "windowing" approach makes the time required to implement an ECO dependent on the size of the change itself, rather than the size of the overall IC, offering significant efficiency gains in the complex and iterative process of modern chip design (Compl. ¶33; ’626 Patent, col. 2:48-53).
Key Claims at a Glance
- The complaint asserts infringement of at least independent Claim 1 (Compl. ¶34).
- Claim 1 is a method claim with the following key steps:
- (a) receiving as input an integrated circuit design;
- (b) receiving as input an engineering change order to the integrated circuit design;
- (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design;
- (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window;
- (e) replacing an area in a copy of the integrated circuit design... with results of the incremental routing to generate a revised integrated circuit design; and
- (f) generating as output the revised integrated circuit design.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 6,436,807 - Method for Making an Interconnect Layer and a Semiconductor Device Including the Same, Issued August 20, 2002
The Invention Explained
- Problem Addressed: The patent addresses a problem in semiconductor fabrication related to Chemical Mechanical Planarization (CMP), a process used to create flat surfaces on a chip layer. CMP is most effective when the material being polished has a uniform density. The patent notes that prior art methods, which often placed "dummy fill" features based on a "predetermined set density," could result in unnecessary fill, leading to increased parasitic capacitance that degrades chip performance (Compl. ¶6; ’807 Patent, col. 2:21-33). It also notes that large variations in pattern density could prevent CMP from adequately planarizing the surface (Compl. ¶40; ’807 Patent, col. 1:67-2:2).
- The Patented Solution: The invention claims a method for creating a layout that improves planarization. The process involves first determining the existing density of "active interconnect features" across different regions of a layout. Then, "dummy fill features" are selectively added to each region specifically to achieve a desired, uniform final density. A key aspect of this method is defining the minimum size of the dummy fill based on the "dielectric layer deposition bias," a physical characteristic of the manufacturing process, to ensure the fill is effective (Compl. ¶8; ’807 Patent, col. 4:20-45, 5:16-25).
- Technical Importance: This approach allows for more intelligent and optimized placement of dummy fill, aiming to achieve the necessary surface planarity for reliable manufacturing while minimizing the negative electrical impact (parasitic capacitance) of the added material (Compl. ¶9; ’807 Patent, col. 2:63-67).
Key Claims at a Glance
- The complaint asserts infringement of at least independent Claim 1 (Compl. ¶42).
- Claim 1 is a method claim with the following key steps:
- (a) determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout; and
- (b) adding dummy fill features to each layout region to obtain a desired density... the adding comprising defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias for a dielectric layer to be deposited over the interconnect layer.
- The complaint does not explicitly reserve the right to assert dependent claims.
III. The Accused Instrumentality
Product Identification
The complaint identifies the accused instrumentalities not as specific end-products, but as the underlying "Accused Processes" that Defendant MACOM uses to design its semiconductor devices (Compl. ¶¶ 50, 64). These processes are allegedly carried out using a variety of industry-standard EDA tools from vendors such as Cadence, Synopsys, and/or Siemens (Compl. ¶50). The complaint names MACOM’s MAXP-37161B crosspoint switch and its ADSP-21487 audio signal processor device as examples of products designed using these allegedly infringing processes (Compl. ¶¶ 1, 63).
Functionality and Market Context
- The relevant functionality of the Accused Processes, as alleged in the complaint, involves performing the steps of the patented methods. For the ’626 Patent, this includes performing incremental routing for ECOs within a defined window and merging the results to generate a revised design (Compl. ¶50). For the ’807 Patent, this includes determining interconnect density and adding dummy fill to achieve uniform planarization during manufacturing (Compl. ¶¶ 64-66).
- The complaint asserts that these design methodologies are used in the production of MACOM's devices in the United States (Compl. ¶¶ 1, 16). The commercial importance is implied through their use in designing MACOM's commercial products. No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; | MACOM's Accused Processes allegedly perform a method for routing only the nets affected by an ECO, which implies the creation of a bounded area or window for the change (Compl. ¶50). | ¶50 | col. 6:25-30 |
| (d) performing an incremental routing... only for each net in the integrated circuit design that is enclosed by the window; | MACOM is alleged to employ design tools (e.g., Cadence, Synopsys) to perform incremental routing as part of implementing an ECO (Compl. ¶50). | ¶50 | col. 6:30-34 |
| (e) replacing an area in a copy of the integrated circuit design... with results of the incremental routing to generate a revised integrated circuit design; and | The complaint alleges that MACOM's processes merge the changed area into the overall circuit layout to generate a revised integrated circuit design (Compl. ¶50). | ¶50 | col. 6:35-41 |
| (f) generating as output the revised integrated circuit design. | The process is alleged to generate a revised integrated circuit design for the MACOM Accused Product (Compl. ¶50). | ¶50 | col. 6:41-42 |
Identified Points of Contention
- Technical Question: The complaint alleges on "information and belief" that MACOM uses third-party EDA tools to perform the claimed steps. A central question will be what evidence demonstrates that MACOM's specific use of these general-purpose tools constitutes the performance of each element of Claim 1, as opposed to other non-infringing design methodologies those tools might also support.
- Scope Question: What is the scope of "performing an incremental routing"? The dispute may turn on whether the routing performed by the accused EDA tools is merely a standard feature or if it operates in the specific, window-based, and replacement-focused manner required by the full context of Claim 1.
’807 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout; | MACOM's Accused Processes allegedly determine an active interconnect feature density for layout regions of its Accused Product by employing a design tool (Compl. ¶65). | ¶65 | col. 4:24-28 |
| (b) adding dummy fill features to each layout region to obtain a desired density... the adding comprising defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias... | MACOM is alleged to add dummy fill to obtain a desired density, with the complaint asserting that this process includes "defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias" (Compl. ¶¶ 66-67). | ¶¶66, 67 | col. 5:16-25 |
Identified Points of Contention
- Technical Question: The allegation for claim element 1(b) is highly specific. The key factual question will be whether MACOM’s process for adding dummy fill actually uses a "dielectric layer deposition bias" as an input to define the fill's minimum dimension. Evidence for this specific calculation, rather than other heuristics for dummy fill, will be critical.
- Scope Question: Does the term "determining an active interconnect feature density" require a specific calculation method, or can it be read broadly to cover any process that assesses layout density before adding fill? The defense may argue that its process does not "determine" density in the manner taught by the patent.
V. Key Claim Terms for Construction
For the ’626 Patent
- The Term: "window"
- Context and Importance: This term is the central concept of the patent. Its construction will determine whether the accused processes, which allegedly use standard EDA tools to isolate and work on portions of a design, fall within the claim's scope. Practitioners may focus on this term because its definition could distinguish the patented method from conventional design partitioning.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification provides a high-level definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 4:59-62). This could support a broad definition covering many forms of design partitioning.
- Evidence for a Narrower Interpretation: The detailed description outlines a specific method for creating the window, which involves identifying port instances for changed nets, calculating bounding boxes, and merging them (’626 Patent, col. 4:57-col. 5:11, FIG. 3). A party could argue the term should be limited by these specific disclosed steps.
For the ’807 Patent
- The Term: "dielectric layer deposition bias"
- Context and Importance: This technical term is the lynchpin of Claim 1(b) and a primary point of novelty asserted by the patent. Infringement hinges on whether the accused process uses this specific physical manufacturing parameter to size dummy fill features.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The complaint does not provide sufficient detail for analysis of evidence that may support a broader interpretation. The term appears to be a specific technical concept without a clear, broader alternative presented in the patent.
- Evidence for a Narrower Interpretation: The specification provides a detailed technical definition, explaining that the bias can be "positive or negative" depending on the deposition process (e.g., HDP-CVD vs. PE-CVD) and is related to whether the resulting "protrusion" in the dielectric material is narrower or wider than the underlying interconnect feature (’807 Patent, col. 2:34-45). This ties the term directly to observable physical phenomena in semiconductor manufacturing.
VI. Other Allegations
- Indirect Infringement: The complaint makes general allegations of direct and indirect infringement (Compl. ¶¶ 55, 69). However, it does not plead specific facts to support a claim of either induced infringement (e.g., knowledge and intent to encourage another's infringement) or contributory infringement (e.g., providing a component with no substantial non-infringing use).
- Willful Infringement: The complaint requests attorneys' fees under 35 U.S.C. § 285, alleging the infringement is "exceptional" (Compl. ¶¶ 56, 70). It does not allege that MACOM had knowledge of the patents before the lawsuit was filed. Therefore, any claim for enhanced damages for willfulness would likely be based on MACOM's alleged continuation of the accused activities after receiving notice of the suit.
VII. Analyst’s Conclusion: Key Questions for the Case
- A central issue will be one of evidentiary proof: On what factual basis does Plaintiff allege that Defendant's use of general-purpose, third-party EDA tools implements the specific methodologies of the patents-in-suit? The case will likely depend on discovery into Defendant’s proprietary design processes to substantiate the "information and belief" pleadings.
- The case also presents a key question of technical specificity: Does the accused "dummy fill" process in fact use the "dielectric layer deposition bias," a specific physical manufacturing parameter, to define fill dimensions as required by Claim 1 of the ’807 patent? Or does it rely on different, more conventional heuristics for controlling layout density?
- Finally, the dispute raises a question of definitional scope: Will the term "window" in the ’626 patent be construed broadly to cover any form of design partitioning common in modern EDA tools, or will it be limited to the specific bounding-box creation method detailed in the patent's embodiment? The outcome of this construction will be critical to the infringement analysis.