DCT
1:22-cv-11839
Bell Semiconductor LLC v. Skyworks Solutions Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Skyworks Solutions, Inc. (California)
- Plaintiff’s Counsel: Arrowood LLP; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 1:22-cv-11839, D. Mass., 10/28/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Massachusetts because Defendant maintains a "regular and established place of business" in the district, including a manufacturing facility in Woburn and a semiconductor design center in Andover, and has committed acts of infringement there.
- Core Dispute: Plaintiff alleges that Defendant’s process for designing semiconductor chips infringes a patent related to methods for efficiently implementing engineering changes in an integrated circuit design.
- Technical Context: The technology concerns electronic design automation (EDA), a field focused on the software tools used to design complex integrated circuits, where minimizing redesign time is critical for time-to-market.
- Key Procedural History: The complaint does not mention any prior litigation, IPR proceedings, or licensing history related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | Priority Date, U.S. Patent No. 7,231,626 |
| 2007-06-12 | Issue Date, U.S. Patent No. 7,231,626 |
| 2022-10-28 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
- Patent Identification: U.S. Patent No. 7,231,626, “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows,” issued June 12, 2007.
The Invention Explained
- Problem Addressed: In conventional integrated circuit (IC) design, implementing even a minor engineering change order (ECO) required design tools to re-process the entire circuit layout. This process was highly inefficient, as "design tool run times typically scale with the size of the entire integrated circuit design," leading to turnaround times of "about one week regardless of the size of the engineering change order" (’626 Patent, col. 2:13-22, 38-41; Compl. ¶25-26).
- The Patented Solution: The invention provides a method to localize the impact of an ECO by creating a "window" that encloses only the portion of the IC design being changed. The method then performs design steps, such as routing, only for the electrical connections ("nets") within that window. The results are then merged back into a copy of the full design, creating a revised layout without re-running the entire process (’626 Patent, Abstract; col. 3:20-24). This avoids "unnecessary re-checking of the all the polygons in the integrated circuit database" (’626 Patent, col. 4:29-32).
- Technical Importance: The method provides "significant savings in the resources required to perform routing, design rule check verification, net delay calculation, and parasitic extraction" by focusing only on incremental changes (’626 Patent, col. 3:20-24).
Key Claims at a Glance
- The complaint asserts infringement of at least Claim 1 (’626 Patent, col. 6:58-7:8; Compl. ¶31).
- Independent Claim 1 breaks down into the following essential elements:
- Receiving an integrated circuit design as input.
- Receiving an engineering change order for the design as input.
- Creating at least one "window" that encloses the change, where the window is smaller than the entire area of the design.
- Performing "incremental routing" of the design only for each net enclosed by the window.
- Replacing the corresponding area in a copy of the design with the results of the incremental routing to create a revised design.
- Generating the revised integrated circuit design as output.
- The complaint does not explicitly assert dependent claims but alleges infringement of functionalities described in them, such as performing a design rule check, parasitic extraction, and net delay calculation only within the ECO window (Compl. ¶40-41).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Processes" as the "patented methodology to design one or more semiconductor devices," including for the "Si5334" product (Compl. ¶1, 38).
Functionality and Market Context
- The complaint alleges that Defendant uses a variety of commercial design tools from vendors like Cadence, Synopsys, and/or Siemens to implement its Accused Processes (Compl. ¶39-41). The accused functionality is the process of performing "incremental routing" to implement an ECO. This involves routing only the nets affected by the change, merging the changed area into the overall layout, and performing related analysis like design rule checks and parasitic extraction only for the nets within the defined ECO window (Compl. ¶39-41). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
Claim Chart Summary
- The complaint provides a narrative infringement theory but does not include the referenced claim chart exhibit (Compl. ¶42). The following table summarizes the allegations for Claim 1 against the Accused Processes.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | Skyworks uses its Accused Processes, which inherently receive an IC design, to design semiconductor devices (Compl. ¶38). | ¶38, ¶39 | col. 6:59 |
| (b) receiving as input an engineering change order to the integrated circuit design; | Skyworks employs design tools to implement an ECO as part of its Accused Processes (Compl. ¶39). | ¶39 | col. 7:1-2 |
| (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design introduced by the engineering change order wherein the window is bounded by coordinates that define an area that is less than an entire area of the integrated circuit design; | The Accused Processes define a limited area for processing, referred to as the "window defining the ECO" or "the ECO window," which is smaller than the full circuit layout (Compl. ¶40-41). | ¶40, ¶41 | col. 7:3-6 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | The Accused Processes "perform a method for only routing the nets affected by the ECO" using a design tool to "perform incremental routing" (Compl. ¶39). | ¶39 | col. 7:7-8 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing to generate a revised integrated circuit design; and | The Accused Processes perform "merging that changed area into the overall circuit layout... to generate a revised integrated circuit design" (Compl. ¶39). | ¶39 | col. 7:9-13 |
| (f) generating as output the revised integrated circuit design. | The Accused Processes generate a "revised integrated circuit design" as the output of implementing an ECO (Compl. ¶39). | ¶39 | col. 7:14-15 |
Identified Points of Contention
- Scope Questions: Do the standard "incremental" or "ECO" features of commercial EDA tools (e.g., from Cadence, Synopsys) inherently practice the steps of "creating at least one window" and "replacing an area in a copy" as recited in the claims, or do the claims require a more specific, non-standard implementation?
- Technical Questions: What evidence does the complaint provide that the Accused Processes perform routing and analysis only for the nets enclosed by the window, as strictly required by the claim? A key question will be whether Defendant's processes perform any operations outside the alleged window that would take them outside the literal scope of the claim.
V. Key Claim Terms for Construction
The Term: "window"
Context and Importance: The "window" is the central inventive concept that enables the claimed efficiency gains. The scope of this term will be critical, as it defines the boundary within which all subsequent claimed operations must occur. Practitioners may focus on this term because the infringement allegation hinges on whether the localized processing areas in Defendant’s EDA tools meet the patent's definition of a "window."
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent provides a general definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 3:59-63). This could be read to cover any method that isolates a sub-region of the chip for processing.
- Evidence for a Narrower Interpretation: The patent describes a specific process for creating the window, which involves calculating a "bounding box" around changed port instances and merging overlapping boxes (’626 Patent, col. 4:57-65, 5:4-7). A defendant could argue that the term should be limited to windows created by this specific algorithm, not just any localized processing area.
The Term: "replacing an area in a copy"
Context and Importance: This term from claim 1(e) describes how the localized changes are integrated into the final design. The precise mechanism is important because if the accused process modifies the design data in a way that is not "replacing an area in a copy," it may not infringe.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes this step in general terms as when "incremental routing changes are merged into the design database" (’626 Patent, col. 4:19-20). This language could support a construction covering various methods of data integration.
- Evidence for a Narrower Interpretation: The claim language specifies replacing an area "in a copy" of the design. A defendant might argue this requires creating a distinct duplicate of the entire design database first, and that a process which modifies the original data "in-place" would not meet this limitation.
VI. Other Allegations
- Indirect Infringement: The complaint does not contain specific allegations of induced or contributory infringement. The focus is on Defendant’s direct infringement by using the patented method (Compl. ¶38).
- Willful Infringement: The complaint does not use the term "willful." However, it alleges that Defendant's infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶45; Prayer for Relief ¶(e)). This allegation is not supported by specific facts detailing pre-suit knowledge of the patent.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technical implementation: Do the commercial EDA tools used in Skyworks' "Accused Processes" operate in a way that maps directly onto the specific steps of the asserted claims? The case may turn on evidence of whether these tools truly perform routing and analysis only within a "window" and integrate the results by "replacing an area in a copy," as the patent requires.
- A central legal question will be one of claim scope: Can the term "window", described in the patent with a specific creation methodology, be construed broadly enough to read on the localized processing regions used by standard, off-the-shelf semiconductor design software? The answer will likely determine whether the use of such software for its intended ECO functions constitutes infringement.
- Finally, an evidentiary question will be whether dependent claim features, such as incremental design rule checks and parasitic extraction (Compl. ¶40-41), are actually performed by the Accused Processes in the limited, window-based manner required by the patent, or if they are performed in a way that is technically distinct from the patented method.