DCT

1:22-cv-12010

Exegy Inc v. NovaSparks SA

Log In

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 1:22-cv-12010, D. Mass., 01/25/2023
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants regularly transact business in the district, Defendant NovaSparks, Inc. is incorporated in Massachusetts, and Defendant NovaSparks SAS is a foreign corporation.
  • Core Dispute: Plaintiff alleges that Defendant’s FPGA-based financial data processing products infringe ten patents related to hardware-accelerated, high-speed processing of financial market information.
  • Technical Context: The technology involves using Field Programmable Gate Arrays (FPGAs) to achieve ultra-low latency in processing high-volume financial market data, a critical capability in the competitive high-frequency trading industry.
  • Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date Event
2005-08-05 Priority Date for ’046, ’081, ’680, ’104, ’249, ’805, ’243 Patents
2011-04-05 U.S. Patent No. 7,921,046 Issues
2012-03-27 Priority Date for ’393, ’196 Patents
2013-06-04 U.S. Patent No. 8,458,081 Issues
2013-07-02 U.S. Patent No. 8,478,680 Issues
2013-11-26 U.S. Patent No. 8,595,104 Issues
2014-06-24 U.S. Patent No. 8,762,249 Issues
2014-07-01 U.S. Patent No. 8,768,805 Issues
2015-06-02 U.S. Patent No. 9,047,243 Issues
2017-02-15 Priority Date for ’453 Patent
2018-06-05 U.S. Patent No. 9,990,393 Issues
2018-11-06 U.S. Patent No. 10,121,196 Issues
2019-03-12 U.S. Patent No. 10,229,453 Issues
2023-01-25 First Amended Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,921,046 - "High Speed Processing of Financial Information Using FPGA Devices," issued April 5, 2011

The Invention Explained

  • Problem Addressed: The patent addresses the challenge of processing massive streams of financial market data at high speeds, a task for which conventional software-based systems face significant latency and throughput limitations (’046 Patent, col. 2:24-34).
  • The Patented Solution: The invention proposes a hybrid system where software logic and firmware logic cooperate. Software logic manages and controls the flow of financial data to and from firmware logic, which is implemented on a reconfigurable device like an FPGA to perform specific, high-speed data processing operations at hardware speeds (’046 Patent, col. 4:5-15). This architecture aims to combine the raw speed of hardware with the flexibility of software control.
  • Technical Importance: This hybrid approach allows for hardware-level performance in latency-critical data processing while retaining the ability for software to flexibly manage data flows and processing tasks, a key architectural advantage in evolving financial markets (’046 Patent, col. 2:54-61).

Key Claims at a Glance

  • The complaint asserts independent claim 9 (Compl. ¶41).
  • Essential elements of claim 9 (a method) include:
    • Controlling, with software logic, a flow of financial market data from the software logic to the firmware logic.
    • Performing a specified financial data processing operation on the financial market data with the firmware logic on a reconfigurable logic device in response to the software logic controlling step.
    • Controlling, with the software logic, a flow of firmware-processed financial market data from the firmware logic to the software logic.
  • The complaint also asserts dependent claims 10, 14, and 15 (Compl. ¶41).

U.S. Patent No. 8,458,081 - "High Speed Processing of Financial Information Using FPGA Devices," issued June 4, 2013

The Invention Explained

  • Problem Addressed: The patent background describes the difficulty in maintaining and updating records for financial instruments in real-time when faced with high-velocity streams of market data messages from multiple sources (’081 Patent, col. 1:15-28).
  • The Patented Solution: The patent discloses a data processing pipeline implemented in firmware on a reconfigurable logic device. This hardware pipeline is designed to directly receive financial market data messages and process each message to update a corresponding stored record for the associated financial instrument, all within the reconfigurable logic device itself (’081 Patent, col. 4:18-35; Compl. ¶47).
  • Technical Importance: By keeping the record update process entirely within the hardware pipeline, the invention seeks to eliminate the latency associated with passing data back and forth between hardware and a host software system for record management (’081 Patent, col. 4:29-35).

Key Claims at a Glance

  • The complaint asserts independent claims 1 and 18 (Compl. ¶49).
  • Essential elements of claim 1 (an apparatus) include:
    • A record memory for storing a plurality of records for a plurality of financial instruments.
    • A reconfigurable logic device configured to:
      • Receive financial market data messages.
      • Retrieve records from the record memory associated with the messages' financial instruments.
      • Process each received message to update the record for the associated financial instrument.
  • The complaint also asserts dependent claim 4 (Compl. ¶49).

U.S. Patent No. 8,478,680 - "High Speed Processing of Financial Information Using FPGA Devices," issued July 2, 2013

  • Technology Synopsis: This patent describes a data processing pipeline on a reconfigurable logic device that processes streaming financial market data. The device specifically maintains real-time order books for a plurality of financial instruments based on incoming messages representing offers to buy and sell (Compl. ¶55).
  • Asserted Claims: Independent claims 1, 9, 11, and 19 (Compl. ¶57).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’680 Patent (Compl. ¶57).

U.S. Patent No. 8,595,104 - "High Speed Processing of Financial Information Using FPGA Devices," issued November 26, 2013

  • Technology Synopsis: The invention concerns a data processing pipeline on a reconfigurable logic device that maintains records for financial instruments. Each stored record includes an "interest list" that identifies which entities have expressed an interest in being notified of updates to that record (Compl. ¶63).
  • Asserted Claims: Independent claims 1 and 30 (Compl. ¶65).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’104 Patent (Compl. ¶65).

U.S. Patent No. 8,762,249 - "Method and Apparatus for High-Speed Processing of Financial Market Depth Data," issued June 24, 2014

  • Technology Synopsis: This patent discloses a ticker plant with a reconfigurable logic device that processes "level 2" financial data, which contains limit order events. The device updates order books, determines if a limit order event modifies the "top" of an order book, and generates a synthesized quote event if it does (Compl. ¶71).
  • Asserted Claims: Independent claim 1 (Compl. ¶73).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’249 Patent (Compl. ¶73).

U.S. Patent No. 8,768,805 - "Method and Apparatus for High-Speed Processing of Financial Market Depth Data," issued July 1, 2014

  • Technology Synopsis: The patent describes a method where a reconfigurable logic device processes streaming limit order events to determine order book data. It then generates a stream of "enriched" limit order events by adding the determined order book data to the original limit order events (Compl. ¶79).
  • Asserted Claims: Independent claims 1, 13, and 21 (Compl. ¶81).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’805 Patent (Compl. ¶81).

U.S. Patent No. 9,047,243 - "Method and Apparatus for Low Latency Data Distribution," issued June 2, 2015

  • Technology Synopsis: This patent details a method for data distribution where a processor generates unique, customized data streams for multiple data consumers. Each stream contains only update events for items of interest to that specific consumer and is distributed via direct memory access (DMA) write operations to shared memories without requiring feedback from the consumers (Compl. ¶87).
  • Asserted Claims: Independent claims 24 and 37 (Compl. ¶89).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’243 Patent (Compl. ¶89).

U.S. Patent No. 9,990,393 - "Intelligent Feed Switch," issued June 5, 2018

  • Technology Synopsis: The invention is an intelligent feed switch for processing financial data, where switching logic and a processor (such as an FPGA, GPU, or CMP) are co-resident. The switch is configured to analyze message data on a consumer-specific basis and repacketize it into outgoing consumer-specific data packets (Compl. ¶95).
  • Asserted Claims: Independent claims 1, 12, 17, 31, and 33 (Compl. ¶97).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’393 Patent (Compl. ¶97).

U.S. Patent No. 10,121,196 - "Offload Processing of Data Packets Containing Financial Market Data," issued November 6, 2018

  • Technology Synopsis: This patent describes an intelligent packet switch that reduces processing latency by embedding data processing operations into the switch itself. The switch's processor determines the data feed for an incoming packet, accesses metadata for parsing that packet, and associates the metadata with the packet (Compl. ¶103).
  • Asserted Claims: Independent claim 1 (Compl. ¶105).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’196 Patent (Compl. ¶105).

U.S. Patent No. 10,229,453 - "Method and System for Low Latency Basket Calculation," issued March 12, 2019

  • Technology Synopsis: The patent discloses a method of streaming financial data through an FPGA with a pipeline configuration. A first hardware module determines basket, price delta, and weight information from messages, and a second downstream module uses this information to compute net asset values (NAVs) for the determined baskets using a delta calculation approach (Compl. ¶111).
  • Asserted Claims: Independent claim 1 (Compl. ¶113).
  • Accused Features: The Accused Products are alleged to practice the claims of the ’453 Patent (Compl. ¶113).

III. The Accused Instrumentality

Product Identification

  • The accused products include NovaSparks’ NovaTick Ticker Plant, NovaTick Appliance, NovaTick Stand-Alone PCIe Card, NovaLink API, NovaSparks API, NovaSparks Wire Format (NSWF), NovaTick NBBO Calculator, and ETF Calculator products (Compl. ¶13).

Functionality and Market Context

  • The complaint alleges these products are "FPGA-based high performance and ultra-low latency trading solutions for financial markets" (Compl. ¶10). Their function is to enable high-speed processing of real-time financial information, delivering normalized market data, including book building and consolidation, in less than one micro-second (Compl. ¶¶11-12). The complaint asserts that these products compete directly with Exegy's patented products and services (Compl. ¶16). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,921,046 Infringement Allegations

Claim Element (from Independent Claim 9) Alleged Infringing Functionality Complaint Citation Patent Citation
A method for processing financial market data using software logic and firmware logic... The Accused Products are systems that use FPGA processors (firmware logic) for high-speed processing of financial information (software logic) (Compl. ¶39, ¶11). ¶39, ¶42 col. 1:15-18
controlling with the software logic a flow of financial market data from the software logic to the firmware logic... The complaint alleges the Accused Products satisfy this limitation by virtue of performing the overall claimed method. ¶39, ¶42 col. 12:47-51
performing a specified financial data processing operation...with the firmware logic on a reconfigurable logic device... The Accused Products perform "normalized market data, including book building and consolidation" using FPGA processors (Compl. ¶12). ¶12, ¶42 col. 12:55-58
controlling with the software logic a flow of firmware-processed financial market data from the firmware logic to the software logic. The complaint alleges the Accused Products satisfy this limitation by virtue of performing the overall claimed method. ¶39, ¶42 col. 12:52-54
  • Identified Points of Contention:
    • Technical Question: The complaint alleges that the Accused Products perform the method of claim 9 but does not provide specific facts explaining how software logic is used to "control" the flow of data to and from the FPGA. A central question will be whether the interaction between software and hardware in the Accused Products meets the specific "controlling" steps required by the claim, or if it constitutes a different, non-infringing architecture.

U.S. Patent No. 8,458,081 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
An apparatus...comprising: a record memory for storing a plurality of records for a plurality of financial instruments... The complaint describes the Accused Products as performing "book building and consolidation" and managing financial data, which suggests the use of stored records for financial instruments (Compl. ¶12). ¶12, ¶50 col. 4:18-20
and a reconfigurable logic device...configured to: receive financial market data messages... The Accused Products are FPGA-based and process "real-time financial market data feeds" which are composed of messages (Compl. ¶13). ¶13, ¶50 col. 4:21-22
retrieve from the record memory the records for the messages' associated financial instruments... The complaint does not provide sufficient detail for analysis of this element. ¶50 col. 4:23-25
and process each received financial market data message to update the record for the financial instrument associated with that message. The Accused Products are alleged to process messages to perform functions like "book building," which inherently involves updating stored records for financial instruments (Compl. ¶12, ¶47). ¶12, ¶47, ¶50 col. 4:26-29
  • Identified Points of Contention:
    • Evidentiary Question: The complaint alleges that the Accused Products update stored records for financial instruments but does not specify where this record memory resides or how the FPGA retrieves from it. A key question for discovery will be to determine the architecture of the Accused Products and what evidence exists that the FPGA itself performs the claimed retrieve-and-update process on a dedicated record memory as required by the claim.

V. Key Claim Terms for Construction

  • For the ’046 Patent:

    • The Term: "controlling with the software logic a flow of financial market data"
    • Context and Importance: This term appears central to defining the interaction between the software and hardware elements. The outcome of the infringement analysis may depend on whether this requires active, dynamic command-and-response management by the software, or if it can be read more broadly to cover a more passive configuration where software simply directs a data stream to the hardware for processing. Practitioners may focus on this term because it distinguishes a potentially inventive interactive system from a simple hardware offload architecture.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification states the invention relates generally to a "data processing platform" where software and firmware logic are "cooperatively functioning," which might suggest any functional cooperation is sufficient (’046 Patent, col. 4:5-8).
      • Evidence for a Narrower Interpretation: The detailed description discusses embodiments where software logic sends "commands" to the firmware and receives "status information" back, suggesting a more specific, command-driven form of control is contemplated (’046 Patent, col. 11:3-10).

  • For the ’081 Patent:

    • The Term: "data processing pipeline"
    • Context and Importance: This term defines the claimed hardware structure. The infringement question may turn on whether the accused FPGA architecture constitutes a "pipeline" as understood by the patent. Practitioners may focus on this term because a defendant could argue its hardware implementation uses a different structure (e.g., a parallel processing array rather than a sequential pipeline) that falls outside the claim's scope.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The patent abstract describes the invention broadly as a reconfigurable logic device that processes messages to update a record, without strictly defining the internal hardware arrangement as a pipeline. This could support an interpretation where any hardware configuration that achieves this result infringes (’081 Patent, Abstract).
      • Evidence for a Narrower Interpretation: The detailed description repeatedly refers to "firmware pipelines" and "pipelined firmware application modules," and Figure 2 depicts a sequential chain of modules. This may support a narrower construction requiring a sequential flow of data through distinct processing stages on the hardware (’081 Patent, col. 4:18-19; Fig. 2).

VI. Other Allegations

  • Willful Infringement: The complaint alleges that Defendants' infringement has been willful for all ten asserted patents (Compl. ¶¶ 44, 52, 60, 68, 76, 84, 92, 100, 108, 116). The complaint does not, however, plead any specific facts to support this allegation, such as pre-suit knowledge of the patents.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of claim construction and technical scope: can terms such as "controlling with the software logic" ('046 Patent) and "data processing pipeline" ('081 Patent) be construed broadly enough to read on the specific hardware and software architecture of the Accused Products? The resolution of these foundational terms will likely impact the infringement analysis for the entire portfolio of asserted patents, which share a common technological basis.
  • A key challenge for the plaintiff will be one of evidentiary proof: the complaint makes conclusory infringement allegations for ten patents while providing minimal public-facing technical evidence mapping the specific operations of the Accused Products to the discrete elements of the asserted claims. The case will likely depend on whether technical evidence uncovered during discovery is sufficient to substantiate these detailed infringement theories, which are currently premised on non-public infringement charts.