DCT
4:22-cv-11388
Bell Semiconductor LLC v. NVIDIA Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Nvidia Corporation (California)
- Plaintiff’s Counsel: McKool Smith, P.C.; Arrowood LLP; Devlin Law Firm LLC
- Case Identification: 4:22-cv-11388, D. Mass., 11/21/2022
- Venue Allegations: Venue is alleged to be proper in the District of Massachusetts because Nvidia maintains a regular and established place of business in Westborough and Westford, employs more than 40 engineers in the state, and advertises for relevant technical positions in the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal processes for designing semiconductor chips infringe two patents related to improving the efficiency of electronic design automation (EDA).
- Technical Context: The technology concerns software methods for validating integrated circuit designs and for inserting non-functional "dummy metal" to ensure manufacturability, both critical steps in modern semiconductor fabrication.
- Key Procedural History: The operative pleading is a First Amended Complaint. The complaint notes that Plaintiff Bell Semic is a successor to the patent portfolios of Bell Labs, Lucent Technologies, Agere Systems, and LSI Corporation.
Case Timeline
| Date | Event |
|---|---|
| 2003-10-10 | ’803 Patent Priority Date |
| 2004-09-22 | ’989 Patent Priority Date |
| 2006-12-12 | ’989 Patent Issue Date |
| 2007-08-21 | ’803 Patent Issue Date |
| 2022-11-21 | First Amended Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,149,989 - "Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design," issued December 12, 2006
The Invention Explained
- Problem Addressed: The patent’s background section describes a dilemma in semiconductor design validation. Performing validation checks late in the design cycle is risky, as discovering a fault can force a costly reset of the entire process (Compl. ¶25; ’989 Patent, col. 2:40-46). However, running a full validation check early on an incomplete design is inefficient, requiring substantial computer processing time and generating a large number of "false positive" errors that are difficult to sort through (Compl. ¶25; ’989 Patent, col. 2:50-58).
- The Patented Solution: The invention proposes a method for targeted, early-stage validation. It involves receiving a comprehensive "physical design rule deck" and then "generating a specific rule deck" from it that includes only rules relevant to a particular class of high-priority errors—"texted metal short circuits" (Compl. ¶27; ’989 Patent, col. 7:16-21). By using this focused, smaller rule set, the system can efficiently identify critical short-circuit flaws early in the design flow without the processing overhead and noise of a full validation run (’989 Patent, col. 2:64-3:11).
- Technical Importance: This method allows for the early detection of significant design defects, which "reduc[es] the computer processing time required to validate an integrated circuit design" and mitigates the risk of costly, late-stage schedule delays (Compl. ¶26; ’989 Patent, col. 3:7-11).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶27).
- Claim 1 breaks down into the following essential elements:
- (a) receiving as input a representation of an integrated circuit design;
- (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design;
- (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits between different signal sources in addition to power and ground in the integrated circuit design; and
- (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits between different signal sources in addition to power and ground in the integrated circuit design.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 7,260,803 - "Incremental Dummy Metal Insertions," issued August 21, 2007
The Invention Explained
- Problem Addressed: The patent addresses inefficiencies related to "dummy fill," a process where non-functional metal pieces are added to a chip design to ensure uniform material density for Chemical Mechanical Polishing (CMP) (Compl. ¶2; ’803 Patent, col. 1:15-22). The problem arises when a late-stage Engineering Change Order (ECO) alters the design. Conventional methods required discarding all previous dummy fill and re-running the entire time-consuming process, which could delay a project by 30 hours or more for a single change (Compl. ¶34; ’803 Patent, col. 1:51-65).
- The Patented Solution: The invention provides an "incremental" method to avoid this delay. After a design change is made, the process does not start over. Instead, it performs a check to see if any pre-existing dummy metal objects now "intersect with any other objects in the design data" (Compl. ¶36; ’803 Patent, col. 6:9-11). If an intersection is found, the system simply "delet[es] the intersecting dummy metal objects," leaving the vast majority of non-intersecting dummy metal in place and thereby "avoiding having to rerun the dummy fill tool" (Compl. ¶36; ’803 Patent, col. 6:12-15).
- Technical Importance: This approach saves significant time in the final stages of a chip design by eliminating the need for a full, computationally expensive rerun of the dummy fill tool after each minor design modification (’803 Patent, col. 2:20-23).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶36).
- Claim 1 breaks down into the following essential elements:
- (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; and
- (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool.
- The complaint does not explicitly reserve the right to assert dependent claims.
III. The Accused Instrumentality
Product Identification
- The complaint accuses Nvidia's internal design methodologies, referred to as the "Accused Processes," which are used to create its semiconductor products, including the GV100-400-A1 device (Compl. ¶¶1, 44, 57). The infringement allegations are directed at the process of using EDA tools from vendors such as Cadence, Synopsys, and/or Siemens, rather than at the final chip as a product (Compl. ¶¶44, 57).
Functionality and Market Context
- The accused functionality for the ’989 Patent involves the use of design tools that include a "short finder" or "short locator" to validate circuit designs against short-circuit rules (Compl. ¶46).
- The accused functionality for the ’803 Patent involves the use of design tools to manage ECOs. After a change, Nvidia allegedly employs a Design Rule Check (DRC) tool to identify and "repair DRC violations associated with shorts caused by dummy fill geometries intersecting with other objects," which may include "trim[ming] metal fill geometries" (Compl. ¶¶58-59).
- The GV100-400-A1 device is identified as an example product created using these allegedly infringing processes, situating the dispute within Nvidia's core business of designing and selling advanced semiconductor chips (Compl. ¶1).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’989 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input a representation of an integrated circuit design | Nvidia employs a design tool into which a circuit design for its GV100-400-A1 device is imported. | ¶44 | col. 7:9-11 |
| (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design | Nvidia employs a design tool that receives various in-design verification processes for concurrent physical design and verification. | ¶45 | col. 7:12-15 |
| (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits... | Nvidia uses a design tool with a "short finder" or "short locator" functionality that allows designers to select for texted metal short circuits. | ¶46 | col. 7:16-21 |
| (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits... | The "short finder" functionality is used to identify texted metal short circuits between different signal nets, including power and ground. | ¶46 | col. 7:22-28 |
- Identified Points of Contention:
- Scope Questions: A central question will be whether using a "short finder" or "short locator" feature within a larger EDA tool constitutes "generating a specific rule deck" that includes "only" rules for short circuits, as required by claim 1(c). The defense may argue that selecting a pre-defined check is not equivalent to the claimed act of "generating" a new, specific, and limited rule deck from a more comprehensive one.
- Technical Questions: What evidence does the complaint provide that Nvidia’s process creates a discrete, subordinate rule deck as a separate artifact, as suggested by the patent's language and flowchart (’989 Patent, Fig. 3, step 308), rather than simply applying a filter to a single, monolithic set of rules?
’803 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data | After an ECO, Nvidia employs a design tool to perform a Design Rule Check (DRC) to determine if there are rule violations, including those related to metal fill geometries intersecting with other objects. | ¶58 | col.6:6-11 |
| (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool | Nvidia uses a design tool that "repairs DRC violations" by allowing designers to "trim metal fill geometries that cause the short or DRC violation." | ¶59 | col. 6:12-15 |
- Identified Points of Contention:
- Scope Questions: The dispute may turn on whether the accused acts of "repair[ing] DRC violations" and "trim[ming] metal fill geometries" meet the claim limitation of "deleting the intersecting dummy metal objects." The defense could argue that "trimming" (partial removal or modification) is distinct from "deleting" (complete removal).
- Technical Questions: Does the complaint provide evidence that the "repair" or "trim" functions in Nvidia's tools operate on the "dummy metal objects" themselves, as opposed to modifying the other design objects to resolve the intersection? The claim is specific to deleting the dummy metal.
V. Key Claim Terms for Construction
For the ’989 Patent:
- The Term: "generating a specific rule deck... wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits"
- Context and Importance: This term defines the core inventive concept. The case’s outcome may depend on whether Nvidia's alleged use of a standard "short finder" tool feature is construed as performing this specific, two-part step. Practitioners may focus on this term because the words "generating" and "only" impose significant structural and limiting requirements on the accused process.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification emphasizes the goal of saving "a substantial amount of computer processing time" and avoiding false reports from an incomplete design (’989 Patent, col. 2:50-58). A party may argue that any method that isolates short-circuit checks to achieve this efficiency—regardless of the precise software mechanism—falls within the spirit of the invention.
- Evidence for a Narrower Interpretation: The claim uses the active verb "generating," and the patent's flowchart depicts this as a discrete step (308) that precedes the validation step (310) (’989 Patent, Fig. 3). The specification also discusses creating "a separate rule deck" (col. 5:11-14), and the word "only" strongly suggests an exclusive, rather than filtered, set of rules.
For the ’803 Patent:
- The Term: "deleting the intersecting dummy metal objects"
- Context and Importance: Infringement hinges on this term, as the complaint alleges that "trimming" and "repairing" geometries satisfy this limitation. The construction of "deleting" will therefore be critical.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The stated purpose of the invention is to "avoid[] having to rerun the dummy fill tool" after a design change (’803 Patent, col. 6:14-15). A party could argue that any action that resolves the intersection and achieves this purpose, such as trimming away the intersecting portion of a dummy object, should be considered equivalent to "deleting" for the purposes of the claim.
- Evidence for a Narrower Interpretation: The plain meaning of "deleting" implies complete removal. The patent's own flowchart shows a decision process that results in the step "Delete the object" (’803 Patent, Fig. 2, step 114). An argument could be made that this supports a narrow construction limited to the removal of the entire object, not its modification.
VI. Other Allegations
- Indirect Infringement: The complaint makes a general reference to infringement under "35 U.S.C. § 271, et seq." (Compl. ¶¶48, 61), but does not plead specific facts to support claims of induced or contributory infringement, such as allegations of specific intent or knowledge of infringement combined with the provision of a non-staple component.
- Willful Infringement: The complaint alleges that Nvidia’s infringement is "exceptional" and seeks attorneys’ fees under 35 U.S.C. § 285 (Compl. ¶¶49, 62). However, it does not allege a factual basis for willfulness, such as pre-suit knowledge of the patents or deliberate copying. The allegations are conclusory.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of process equivalence: for the ’989 patent, does using a standard "short finder" feature in a commercial EDA tool constitute the specific, structured method of "generating a specific rule deck" containing "only" rules for certain errors, or is there a fundamental mismatch between the patent’s explicit methodology and the accused process?
- The case will also likely turn on a question of definitional scope: for the ’803 patent, can the claim term "deleting the intersecting dummy metal objects" be construed to encompass the accused acts of "trimming" geometries or "repairing" design rule violations, or does the claim require complete removal of the object?
- A key evidentiary challenge for the plaintiff will be to prove, based largely on "information and belief," that Nvidia's confidential, internal design workflows using third-party software tools perform the precise steps recited in the asserted method claims.