DCT
4:22-cv-11700
Bell Semiconductor LLC v. NVIDIA Corp
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: NVIDIA Corporation (California)
- Plaintiff’s Counsel: ARROWOOD LLP; DEVLIN LAW FIRM LLC; MCKOOL SMITH, P.C.
- Case Identification: 4:22-cv-11700, D. Mass., 10/05/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Massachusetts because NVIDIA maintains a regular and established place of business in the district, employs engineers involved in the relevant technology there, and commits alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal processes for designing semiconductor chips infringe a patent related to methods for efficiently implementing engineering change orders.
- Technical Context: The technology concerns electronic design automation (EDA), a field focused on software tools that automate the complex and lengthy process of designing integrated circuits.
- Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | ’626 Patent Priority Date (Filing) |
| 2007-06-12 | ’626 Patent Issued |
| 2022-10-05 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - "Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows," issued June 12, 2007
The Invention Explained
- Problem Addressed: The patent's background section describes a significant inefficiency in conventional integrated circuit (IC) design. When a small revision, or "engineering change order" (ECO), is required, the entire multi-million-cell IC design must be processed again through time-consuming steps like routing, design rule checking, and timing analysis, even if the change affects only a tiny fraction of the circuit (Compl. ¶¶2-3; ’626 Patent, col. 2:15-22). This process could take approximately one week, regardless of the change's magnitude, creating a major bottleneck in development (’626 Patent, col. 2:37-44).
- The Patented Solution: The invention solves this problem by creating a virtual "window" that spatially encloses only the portion of the IC design affected by the ECO. Instead of re-running design tools on the entire circuit, the patented method performs the necessary steps, such as "incremental routing," exclusively on the electronic "nets" contained within this window. The updated window contents are then merged back into a copy of the original design to create a revised version, thereby localizing the workload and dramatically reducing processing time (’626 Patent, Abstract; col. 3:25-42).
- Technical Importance: By localizing design revisions, the invention claims to provide "significant savings in the resources required to perform routing, design rule check verification, net delay calculation, and parasitic extraction," which directly translates to faster time-to-market for complex semiconductor devices (’626 Patent, col. 3:19-23).
Key Claims at a Glance
- The complaint asserts infringement of "one or more claims" of the ’626 patent, with a focus on the methodology recited in independent Claim 1 (Compl. ¶37, ¶30). The patent also includes independent Claim 5, which claims a computer-readable storage medium embodying the method steps of Claim 1.
- The essential elements of independent Claim 1 are:
- (a) receiving as input an integrated circuit design;
- (b) receiving as input an engineering change order;
- (c) creating at least one "window" that encloses the change and is smaller than the entire circuit area;
- (d) performing an "incremental routing" of the design "only for each net... that is enclosed by the window";
- (e) replacing the area bounded by the window in a copy of the design with the results of the incremental routing; and
- (f) generating the revised design as output.
III. The Accused Instrumentality
Product Identification
- The complaint accuses NVIDIA's internal design methodologies, referred to as the "Accused Processes," which are used to design its semiconductor products (Compl. ¶38). The NVIDIA GV100-400-A1 device is identified as one example of a product designed using these allegedly infringing processes (Compl. ¶1).
Functionality and Market Context
- The complaint alleges that NVIDIA uses its Accused Processes to "perform a method for only routing the nets affected by the ECO and merging that changed area into the overall circuit layout" (Compl. ¶38). It further alleges that these processes, which may be implemented using third-party EDA tools from vendors such as Cadence, Synopsys, or Siemens, perform critical design steps like parasitic extraction and design rule checks only for nets within a "window" defined by the ECO (Compl. ¶¶38-40).
- The complaint alleges that NVIDIA derives "substantial revenues from its infringing acts" but does not provide specific market data for the accused products or processes (Compl. ¶18).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | NVIDIA's design process begins with an integrated circuit design as an input for its design tools (Implied). | ¶38 | col. 6:56-57 |
| (b) receiving as input an engineering change order to the integrated circuit design; | NVIDIA implements an Engineering Change Order ("ECO") within its design process. | ¶38 | col. 6:58-59 |
| (c) creating at least one window in the integrated circuit design that encloses a change... wherein the window is bounded by coordinates that define an area that is less than an entire area... | NVIDIA's processes define a "window" enclosing the ECO to perform localized parasitic extraction and design rule checks. | ¶¶39-40 | col. 6:60-65 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | NVIDIA is alleged to perform a method "for only routing the nets affected by the ECO." | ¶38 | col. 7:1-4 |
| (e) replacing an area in a copy of the integrated circuit design that is bounded by the coordinates of the window with results of the incremental routing... | NVIDIA is alleged to merge the "changed area into the overall circuit layout." | ¶38 | col. 7:5-9 |
| (f) generating as output the revised integrated circuit design. | NVIDIA's process generates a "revised integrated circuit design." | ¶38 | col. 7:10-11 |
- Identified Points of Contention:
- Scope Questions: The complaint alleges NVIDIA performs the patented method by using third-party EDA tools (Compl. ¶¶38-40). This raises the question of whether NVIDIA's use of these commercially available tools to perform a design task constitutes "performing" each specific, ordered step of the claimed method, or if the functionality resides primarily within the third-party tools in a manner that does not map directly onto the claim limitations.
- Technical Questions: Claim 1 requires "performing an incremental routing... only for each net... that is enclosed by the window." A central evidentiary question will be whether the Accused Processes, as implemented with commercial EDA tools, are strictly limited to the nets within the defined window. The defense may argue that the tools' algorithms perform ancillary calculations or checks on nets outside the window, which would suggest a mismatch with the claim's negative "only" limitation.
V. Key Claim Terms for Construction
- The Term: "window"
- Context and Importance: This term is the central pillar of the invention, defining the localized area where work is performed. The construction of "window" will be critical to determining whether NVIDIA's alleged use of bounded design areas falls within the scope of the claims. Practitioners may focus on this term because the entire infringement case rests on the allegation that NVIDIA's design process creates and uses a "window" as claimed.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification defines a "window" functionally as a "rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 4:59-62). This could support a broad construction covering any method of spatially isolating a portion of the design for processing.
- Evidence for a Narrower Interpretation: The patent also describes a specific algorithm for creating the window, which involves calculating bounding boxes around changed port instances and merging them (’626 Patent, col. 4:61-col. 5:11; Fig. 3). A party could argue the term should be limited to a window created by this or a similar, more structured process.
- The Term: "performing an incremental routing... only for each net... that is enclosed by the window"
- Context and Importance: The word "only" creates a strict negative limitation. Infringement requires that the routing step be exclusively confined to nets within the window. The case may turn on factual evidence about the precise operation of the EDA tools NVIDIA uses.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A plaintiff may argue that the term's purpose, in the context of the patent, is to distinguish the invention from the prior art that re-routes the "entire integrated circuit design" (’626 Patent, col. 2:64-65). Under this view, minor or incidental operations on nets outside the window might not defeat the "only" limitation if the substantive routing work is confined as claimed.
- Evidence for a Narrower Interpretation: A defendant will likely argue for a strict, literal reading. The plain meaning of "only" is "solely" or "exclusively." Any evidence that the accused process performs routing operations, however minor, on nets outside the window could be used to argue for non-infringement.
VI. Other Allegations
- Indirect Infringement: The complaint includes a conclusory allegation of direct and indirect infringement (Compl. ¶43). However, it does not plead specific facts to support a claim of either induced or contributory infringement, such as allegations that NVIDIA instructs others to infringe or provides a component with knowledge and intent that it be used to infringe.
- Willful Infringement: The complaint does not plead facts to support a claim of willful infringement, such as alleging that NVIDIA had pre-suit knowledge of the ’626 patent. The prayer for relief seeks attorneys' fees for an "exceptional" case under 35 U.S.C. § 285, but the complaint body currently lacks the factual predicate for such a finding based on willfulness (Compl. ¶44).
VII. Analyst’s Conclusion: Key Questions for the Case
- A key question will be one of process attribution: where the accused infringement is the use of sophisticated, third-party EDA software, the court will need to determine whether NVIDIA's configuration and operation of these tools constitutes "performing" the specific, ordered method steps of Claim 1, or if the functionality operates in a way that does not align with the claim limitations.
- The case will also present a central question of technical scope: does the negative limitation "only for each net... enclosed by the window" require absolute, 100% exclusion of all routing operations outside the window, or can it be met if the accused process substantially confines its primary routing to the window? The answer will depend on both claim construction and a detailed factual analysis of how the accused EDA tools function in practice.