DCT
2:17-cv-07621
Tessera Advanced Tech Inc v. Samsung Electronics America Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Tessera Advanced Technologies, Inc. (Delaware)
- Defendant: Samsung Electronics America, Inc. (New York) and Samsung Electronics Co., Ltd. (Republic of Korea)
- Plaintiff’s Counsel: Latham & Watkins LLP
- Case Identification: 2:17-cv-07621, D.N.J., 09/28/2017
- Venue Allegations: Venue is alleged to be proper for Samsung Electronics America, Inc. based on its principal place of business being located in the District of New Jersey, and for Samsung Electronics Co., Ltd. as a foreign entity.
- Core Dispute: Plaintiff alleges that certain power management integrated circuits within Samsung's Galaxy S6, S7, and S8 smartphones infringe two patents related to the structure of semiconductor packaging.
- Technical Context: The technology concerns wafer-level packaging (WLP), a method for creating robust and miniaturized electrical connections on semiconductor chips, which is critical for high-performance mobile devices.
- Key Procedural History: The complaint notes that the asserted patents are the subject of a concurrent action filed at the International Trade Commission. It also discloses that U.S. Patent No. 6,954,001 is involved in separate litigation against Broadcom in the District of Delaware and is the subject of a pending, but not yet instituted, petition for inter partes review filed by Broadcom. Plaintiff alleges that Samsung has had knowledge of the asserted patents since a presentation on May 2, 2016, a fact central to the willfulness allegations.
Case Timeline
| Date | Event |
|---|---|
| 2001-12-20 | Earliest Priority Date for '001 and '557 Patents |
| 2004-08-31 | U.S. Patent No. 6,784,557 Issues |
| 2005-10-11 | U.S. Patent No. 6,954,001 Issues |
| 2016-05-02 | Alleged date of Samsung's knowledge of the Asserted Patents |
| 2017-09-28 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,954,001 - Semiconductor Device Including a Diffusion Layer (Issued Oct. 11, 2005)
The Invention Explained
- Problem Addressed: The patent's shared specification with the '557 patent addresses a reliability issue in semiconductor packaging where tin (Sn) from a solder ball connection diffuses into the underlying copper (Cu) wiring on a chip, forming a brittle copper-tin alloy layer that is susceptible to cracking under thermal stress (U.S. Patent No. 6,784,557, col. 1:12-28).
- The Patented Solution: This invention claims a specific structural arrangement to counteract this weakness. It describes a semiconductor device with a first electrode (e.g., copper) and a second electrode (e.g., a tin-containing solder ball) connected to it ('001 Patent, Abstract). The key inventive concept is the dimensional requirement for the resulting structure: the combined thickness of the first electrode portion and the intermediate "diffusion layer" (the copper-tin alloy) must be within the specific range of 10 µm to 20 µm ('001 Patent, col. 27:7-11). This ensures that the overall connection point is thick enough to maintain mechanical integrity despite the presence of the weaker alloy.
- Technical Importance: The claimed structure provides a method for enhancing the thermomechanical reliability of wafer-level chip-scale packages (WLCSPs), a foundational technology for manufacturing the compact and durable integrated circuits required for modern mobile electronics (’557 Patent, col. 1:1-11).
Key Claims at a Glance
- The complaint asserts independent claim 10 (Compl. ¶14).
- The essential elements of claim 10 are:
- A semiconductor device comprising a semiconductor element;
- A first electrode portion on the semiconductor element comprising a first metal component;
- A second electrode portion on the semiconductor element, electrically connected to the first, comprising a second, different metal component; and
- A diffusion layer between the first and second electrode portions, comprising both metal components, where the combined thickness of the first electrode portion and the diffusion layer is in the range of 10 µm to 20 µm.
- The complaint indicates the allegations are exemplary, reserving the right to assert other claims (Compl. ¶10).
U.S. Patent No. 6,784,557 - Semiconductor Device Including a Diffusion Layer Formed Between Electrode Portions (Issued Aug. 31, 2004)
The Invention Explained
- Problem Addressed: As the parent of the ’001 patent, this patent addresses the identical problem of mechanical failure in solder connections due to the formation of a weak copper-tin alloy layer under thermal cycling (’557 Patent, col. 1:12-28).
- The Patented Solution: The ’557 patent offers a related but distinct solution focused on the initial geometry of the electrode. It claims a semiconductor device where the "first electrode portion"—the part of the on-chip wiring that serves as the external connection pad—itself has a thickness in the range of 10 µm to 20 µm (’557 Patent, col. 26:7-9). The principle is that by starting with a sufficiently thick and robust copper pad, the connection can withstand the partial conversion of its material into the weaker alloy layer without compromising the overall structural integrity of the joint (’557 Patent, col. 2:59-67).
- Technical Importance: This approach provided a direct structural specification for designing more reliable solder bump interconnects, facilitating the continued miniaturization and improved durability of semiconductor devices (’557 Patent, col. 1:1-11).
Key Claims at a Glance
- The complaint's detailed allegations map to independent claim 1, despite a potential typographical error referencing claim 10 in the infringement count heading (Compl. ¶24, ¶27).
- The essential elements of claim 1 are:
- A semiconductor device comprising a semiconductor element; and
- A first electrode portion formed on the semiconductor element,
- Wherein the first electrode portion has a thickness in the range of 10 µm to 20 µm.
- The complaint reserves the right to assert other claims (Compl. ¶10).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Samsung's Galaxy S6, S7, and S8 devices, and specifically the Samsung S2MPB02 power management integrated circuit (PMIC) contained within them (Compl. ¶11).
Functionality and Market Context
- The S2MPB02 is a PMIC that utilizes wafer-level packaging ("WLP") to manage its external connections (Compl. ¶11). PMICs are essential components in smartphones and other mobile devices, responsible for controlling and distributing power from the battery to various subsystems. The complaint provides photographs showing the top and bottom of an S2MPB02 chip, illustrating the array of solder connections at issue. This photograph shows the solder ball grid array on the bottom of the S2MPB02 chip that facilitates its connection within the accused smartphones (Compl. ¶11, p. 4).
IV. Analysis of Infringement Allegations
U.S. Patent No. 6,954,001 Infringement Allegations
| Claim Element (from Independent Claim 10) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a semiconductor device, comprising: a semiconductor element; | The accused S2MPB02 PMIC is a semiconductor device that includes a silicon substrate with an integrated circuit. The complaint provides a scanning electron microscope (SEM) image as evidence (Compl. ¶16, p. 6). | ¶15-16 | col. 8:7-9 |
| a first electrode portion formed on the semiconductor element, said first electrode portion comprising a first metal component; | The S2MPB02 allegedly includes a first electrode portion on its silicon substrate that comprises copper (Cu), as shown in an annotated SEM image and supported by energy dispersive x-ray spectrometry (EDS) analysis (Compl. ¶17, p. 6). | ¶17 | col. 8:54-56 |
| a second electrode portion formed on the semiconductor element and electrically connected to said first electrode portion, said second electrode portion comprising a second metal component...; | The S2MPB02 allegedly includes a solder ball comprising tin (Sn) that is formed on the silicon substrate and is electrically connected to the first electrode portion (Compl. ¶18). An annotated SEM image identifies this "second electrode portion" (Compl. ¶18, p. 7). | ¶18 | col. 9:22-25 |
| a diffusion layer formed between said first electrode portion and said second electrode portion... and said first electrode portion and said diffusion layer have a combined thickness in the range of 10 µm to 20 µm. | A diffusion layer, identified as a "copper-tin layer," is allegedly formed between the copper electrode and the solder ball. The complaint provides an annotated SEM image with measurements purporting to show that the combined thickness of this diffusion layer and the first electrode portion is within the 10-20 µm range (Compl. ¶19, p. 9). | ¶19 | col. 10:27-31 |
U.S. Patent No. 6,784,557 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A semiconductor device, comprising: a semiconductor element; and | The accused S2MPB02 PMIC is a semiconductor device comprising a silicon substrate with an integrated circuit (Compl. ¶25-26). | ¶25-26 | col. 26:1-2 |
| a first electrode portion formed on the semiconductor element, | The S2MPB02 allegedly includes a first electrode portion formed on the silicon substrate (Compl. ¶27). | ¶27 | col. 26:3-4 |
| wherein said first electrode portion has a thickness in the range of 10 µm to 20 µm. | The complaint alleges that the first electrode portion in the S2MPB02 has a thickness within this range. It presents an annotated SEM image of the device's cross-section with measurements of a 5.2 µm "copper" layer and a 5.1 µm "copper layer," which sum to 10.3 µm (Compl. ¶27, p. 12). | ¶27 | col. 26:7-9 |
- Identified Points of Contention:
- Scope Questions: A central dispute may arise over the definition of the "first electrode portion." The complaint's evidence for the ’557 patent relies on summing the thicknesses of two distinct layers identified in an SEM image ("copper" and "copper layer") to meet the 10 µm minimum. The defense may argue that the claim term "a first electrode portion" reads on only one of these layers, which would fall below the claimed thickness range.
- Technical Questions: For the ’001 patent, a key question will be whether the layer identified as the "copper-tin layer" in the complaint's visuals is, in fact, the "diffusion layer" as contemplated by the patent. The analysis will depend on expert interpretation of the material composition and formation process of this layer in the accused device versus the teachings of the patent specification.
V. Key Claim Terms for Construction
- The Term: "first electrode portion" (in asserted claims of both patents)
- Context and Importance: The construction of this term is fundamental to the infringement analysis for both patents, as the claimed thickness limitations directly apply to it. Practitioners may focus on this term because the plaintiff's infringement theory appears to depend on combining multiple sub-layers to meet the dimensional requirement, raising the question of what constitutes a single "portion."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes an "external electrode portion" as the part of a "metal wiring" that "functions as an external electrode" (’557 Patent, col. 1:54-57). This functional language may support an interpretation where multiple conductive layers working together to form the connection point constitute a single "portion."
- Evidence for a Narrower Interpretation: The specification also describes a process where a thicker "external electrode portion (14a)" is formed upon a thinner "metal wiring (14)" (’557 Patent, col. 8:36-52; FIG. 1). This could support an argument that the "portion" is a discrete, subsequently formed structure, rather than the entire conductive stack.
- The Term: "diffusion layer" (’001 Patent, Claim 10)
- Context and Importance: The identity and thickness of this layer are dispositive for infringement of the ’001 patent. The dispute will likely center on whether the intermetallic layer in the accused device matches the description and formation process of the "diffusion layer" in the patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification describes the problem as tin from a solder ball "diffus[ing] into Cu of the metal wiring ... to form a Sn-Cu alloy layer" (’557 Patent, col. 1:12-15). This suggests that any intermetallic alloy layer formed at the interface of tin and copper could meet the definition.
- Evidence for a Narrower Interpretation: The specification notes that this "Sn-Cu alloy grows in the most part of the metal wiring" (’557 Patent, col. 1:17-18). A party could argue this implies a specific extent or character of diffusion that must be present in the accused device for its corresponding layer to be considered a "diffusion layer" under the claim.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement for both patents, asserting that Samsung had knowledge of the patents as of at least May 2, 2016, from a presentation by the plaintiff (Compl. ¶21, ¶29). The complaint further alleges that Samsung actively encourages infringement through its marketing materials, technical specifications, data sheets, and user manuals for the accused Galaxy products (Compl. ¶20, ¶28).
- Willful Infringement: Willfulness is alleged for both patents. The allegations are based on Samsung's alleged continuation of infringing activities despite having received actual notice of the patents and the alleged infringement on May 2, 2016, which Plaintiff contends makes the ongoing infringement objectively reckless (Compl. ¶21, ¶29).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of structural definition: can the claim term "a first electrode portion" be construed to encompass the composite, multi-layer copper structure identified in the plaintiff’s evidence, or is it limited to a single, discrete layer? The answer may determine whether the dimensional requirements of both asserted patents are met.
- A central evidentiary question will be one of technical identity and measurement: does the plaintiff’s SEM and EDS evidence prove that the accused S2MPB02 chip contains structures that are technically and dimensionally equivalent to the "diffusion layer" and "first electrode portion" as claimed, particularly when the infringement case for both patents appears to rest on measurements that are very close to the 10 µm lower bound of the claimed ranges?
- A key question for willfulness and inducement will be one of intent: will the plaintiff’s evidence of a May 2, 2016 presentation be sufficient to prove that Samsung had the requisite pre-suit knowledge and specific intent to encourage infringement, thereby supporting the claims for enhanced damages and indirect infringement?