Cedar Lane Tech Inc v. ISS Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Cedar Lane Technologies Inc. (Canada)
  • Defendant: ISS Corp. (New Jersey)
  • Plaintiff’s Counsel: Napoli Shkolnik, LLC; Rabicoff Law LLC
• Case Identification: 2:22-cv-05082, D.N.J., 08/17/2022
• Venue Allegations: Venue is alleged to be proper based on Defendant being incorporated in New Jersey with an established place of business in the district, where acts of infringement have allegedly occurred.
• Core Dispute: Plaintiff alleges that Defendant’s unspecified products infringe three patents related to methods and modules for interfacing digital image sensors with data compression and processing systems.
• Technical Context: The technology addresses the efficient transfer of data from an image sensor to processing components, a foundational function in digital cameras, scanners, and other imaging devices.
• Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit. The allegations of knowledge for indirect and willful infringement are based solely on the filing of this complaint.

Case Timeline

Date	Event
1999-06-01	Priority Date for U.S. Patent No. 6,473,527
2000-01-21	Priority Date for U.S. Patent Nos. 6,972,790 and 8,537,242
2002-10-29	U.S. Patent No. 6,473,527 Issued
2005-12-06	U.S. Patent No. 6,972,790 Issued
2013-09-17	U.S. Patent No. 8,537,242 Issued
2022-08-17	Complaint Filed

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," Issued October 29, 2002

The Invention Explained

• Problem Addressed: The patent’s background describes that conventional systems for JPEG image compression often required an extra memory device, such as RAM, to act as a buffer between the analog-to-digital (A/D) converter and the JPEG compression hardware ('527 Patent, col. 1:47-57). This extra component added to the system's cost and complexity ('527 Patent, col. 1:55-57).
• The Patented Solution: The invention proposes an interface module that eliminates the need for this extra memory buffer ('527 Patent, col. 2:1-4). The module contains its own memory device specifically sized to store the same number of image lines as the internal buffer of the downstream JPEG compression device (e.g., 8 lines for an 8x8 pixel block) ('527 Patent, col. 2:8-12; col. 3:5-8). This allows the module to receive image data line-by-line, assemble a complete data block, and then transmit that block directly to the compression device in the required format, obviating the intermediate, general-purpose RAM ('527 Patent, Abstract).
• Technical Importance: This design sought to reduce the hardware cost and simplify the architecture of digital imaging devices like scanners by removing a redundant memory component ('527 Patent, col. 2:21-23).

Key Claims at a Glance

• The complaint does not specify which claims are asserted, instead referring to "Exemplary '527 Patent Claims" in an external exhibit (Compl. ¶13). Independent claim 1 is a representative apparatus claim.
• Essential elements of Independent Claim 1 include:
  • "read control means" for sequentially reading a predetermined number of image lines from an A/D converter's data output and generating a control signal.
  • "memory means" coupled to the read control means, for storing the predetermined number of image lines, where the memory is "capable of storing the same number of image lines as said built-in memory device" of the JPEG compression means.
  • "output control means" that responds to the control signal to sequentially read an image block from the memory means and forward it to the JPEG compression means' built-in memory.

U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," Issued December 6, 2005

The Invention Explained

• Problem Addressed: The patent identifies an incompatibility between the continuous, video-style data stream from a CMOS image sensor and the random-access data interface of a typical microprocessor ('790 Patent, col. 1:47-54). Bridging this gap conventionally required "additional glue logic" and memory, which undermined the cost and integration advantages of using CMOS technology ('790 Patent, col. 1:50-51, 1:63-66).
• The Patented Solution: The patent describes an interface, preferably integrated on the same semiconductor die as the image sensor, that decouples the sensor and the processor ('790 Patent, col. 2:25-30). The interface uses a memory buffer (such as a FIFO) to store image data as it arrives from the sensor at a fixed rate ('790 Patent, Abstract). When the amount of data in the buffer reaches a predetermined level, a signal generator alerts the host processor system (e.g., via an interrupt or a bus request), which can then read the buffered data at its own rate ('790 Patent, col. 2:6-13).
• Technical Importance: This architecture enables a direct and efficient connection between a CMOS image sensor and a host processor, facilitating the creation of more highly integrated and cost-effective digital imaging systems ('790 Patent, col. 2:25-30).

Key Claims at a Glance

• The complaint does not specify which claims are asserted, referring to "Exemplary '790 Patent Claims" in an external exhibit (Compl. ¶19). Independent claim 1 is a representative apparatus claim.
• Essential elements of Independent Claim 1 include:
  • "a memory" for storing imaging array data and clocking signals at a rate determined by the clocking signals.
  • "a signal generator" for generating a signal for transmission to the processor system "in response to the quantity of data in the memory."
  • "a circuit" for controlling the transfer of data from the memory at a rate determined by the processor system.

U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," Issued September 17, 2013

Technology Synopsis

• As a divisional of the application leading to the '790 patent, the '242 patent addresses the same technical problem of efficiently interfacing an image sensor with a processor system ('242 Patent, col. 1:11-14). The described solution similarly involves an interface with a memory buffer that stores incoming image data and generates a signal to the processor system when a certain quantity of data is ready for transfer, thereby decoupling the fixed data rate of the sensor from the variable-rate operations of the processor ('242 Patent, Abstract).

Asserted Claims

• The complaint does not identify specific asserted claims (Compl. ¶28).

Accused Features

• The complaint does not provide sufficient detail for analysis of accused features, alleging only that unspecified "Exemplary Defendant Products" practice the claimed technology as shown in an external exhibit (Compl. ¶¶ 28, 33).

III. The Accused Instrumentality

Product Identification

• The complaint does not identify any specific accused products, methods, or services by name. It refers generally to "Exemplary Defendant Products" that are purportedly identified in claim chart exhibits attached to the complaint (Compl. ¶¶ 13, 19, 28).

Functionality and Market Context

• The complaint provides no description of the technical functionality, features, or market position of the accused instrumentalities. It alleges in a conclusory manner that the products "practice the technology claimed" by the patents-in-suit (Compl. ¶¶ 15, 24, 33). No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

The complaint's infringement allegations consist entirely of incorporating by reference external claim chart exhibits (Exhibits 4, 5, and 6), which were not included with the filed complaint document (Compl. ¶¶ 16, 25, 34). The complaint provides no narrative summary or factual detail regarding its infringement theory. Therefore, a claim chart summary cannot be constructed.

• Identified Points of Contention:
  • '527 Patent: A central issue will be whether the architecture of an accused product maps onto the "means-plus-function" language of the claims. This raises the question of whether the product contains discrete components corresponding to the "read control means", "memory means", and "output control means" as described in the patent's specification, or if it utilizes a different, more integrated architecture. The scope of these terms will be limited to the corresponding structures disclosed in the patent ('527 Patent, Fig. 2; col. 3:1-18).
  • '790 Patent: The infringement analysis will likely focus on the claimed "signal generator". A key technical question is whether the accused product's interface alerts the processor "in response to the quantity of data in the memory," as the claim requires. This suggests a dispute over the triggering mechanism—specifically, whether the alert is based on a data-level threshold, as described in the patent ('790 Patent, col. 6:11-14), or on another event, such as a processor-initiated poll.

V. Key Claim Terms for Construction

• Term: "memory means... capable of storing the same number of image lines as said built-in memory device" ('527 Patent, Claim 1)

  • Context and Importance: This term defines the core structural feature alleged to be novel over the prior art. The infringement and validity analyses will depend on whether this requires a strict 1:1 correspondence in line-storage capacity between the interface's memory and the JPEG device's internal memory.
  • Evidence for a Broader Interpretation: The use of "capable of storing" could suggest that the memory need only have the ability to be configured this way, not that it is always used in this manner.
  • Evidence for a Narrower Interpretation: The specification repeatedly emphasizes this direct correspondence. For example, it states, "the memory device 24 can save the same number of image lines as that of the memory device 271 built in the JPEG compression device 27" ('527 Patent, col. 3:3-6). The embodiment describes storing "8 lines of image data" to match an 8x8 pixel compression unit, reinforcing a narrow, purpose-built interpretation ('527 Patent, col. 3:6-8).

• Term: "signal generator for generating a signal... in response to the quantity of data in the memory" ('790 Patent, Claim 1)

  • Context and Importance: This term is critical for defining how the patented interface communicates with the host processor. Practitioners may focus on this term because the dispute will likely turn on whether the accused device's communication protocol is triggered by the amount of data in a buffer.
  • Evidence for a Broader Interpretation: The specification discloses multiple types of signals, including an "interrupt signal" and a "bus request signal," which could support a construction covering any signaling method that alerts the processor ('790 Patent, col. 2:14-18).
  • Evidence for a Narrower Interpretation: The detailed description shows the signal generator (48) operating by comparing a "FIFO counter output Sc" with a "FIFO limit Sl" ('790 Patent, col. 6:11-14). This could support a narrower construction limited to mechanisms that actively track data quantity against a pre-set threshold.

VI. Other Allegations

• Indirect Infringement:
  • The complaint alleges induced infringement of the '790 and '242 patents. The factual basis alleged is that Defendant distributes "product literature and website materials inducing end users and others to use its products in the customary and intended manner that infringes" the patents (Compl. ¶¶ 22-23, 31-32). No allegations of indirect infringement are made for the '527 patent.
• Willful Infringement:
  • The complaint alleges that Defendant has had "Actual Knowledge of Infringement" of the '790 and '242 patents since "the service of this Complaint" (Compl. ¶¶ 21, 30). This frames the willfulness allegation as being based on post-filing conduct only. No facts supporting pre-suit knowledge or willfulness are alleged for any of the patents-in-suit.

VII. Analyst’s Conclusion: Key Questions for the Case

• A threshold issue will be the sufficiency of the pleadings. Given that the complaint's infringement allegations rely entirely on conclusory statements that incorporate by reference external exhibits not filed with the court, a central question is whether the pleading provides plausible factual content required to survive a motion to dismiss.
• A core technical issue for the '527 patent will be one of architectural correspondence. Can the patentee show that the accused products contain the specific, structurally-distinct functional "means" required by the claims, or does their architecture differ in a way that avoids infringement of the means-plus-function limitations?
• For the '790 and '242 patents, a key evidentiary question will be one of functional trigger. Does the accused interface alert the host processor "in response to the quantity of data in the memory" as claimed, or is the communication between the imaging and processing components initiated by a different mechanism, such as processor polling, that falls outside the claim scope?