DCT
2:22-cv-05091
Cedar Lane Tech Inc v. Hanwha Techwin America Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Cedar Lane Technologies Inc. (Canada)
- Defendant: Hanwha Techwin America, Inc. (New Jersey)
- Plaintiff’s Counsel: Napoli Shkolnik, LLC; Rabicoff Law LLC
- Case Identification: 2:22-cv-05091, D.N.J., 08/17/2022
- Venue Allegations: Venue is asserted based on Defendant being incorporated in and having an established place of business in the District of New Jersey.
- Core Dispute: Plaintiff alleges that Defendant’s security cameras and related imaging products infringe three patents related to methods for efficiently interfacing image sensors with memory and processing components.
- Technical Context: The patents address fundamental challenges in digital imaging, specifically how to manage the flow of data from an image sensor to compression hardware or a host processor without requiring costly external memory or creating data bottlenecks.
- Key Procedural History: The complaint does not mention any prior litigation, inter partes review proceedings, or licensing history related to the patents-in-suit. The U.S. Patent No. 8,537,242 is a divisional of the application that led to U.S. Patent No. 6,972,790.
Case Timeline
| Date | Event |
|---|---|
| 1999-06-01 | Priority Date for U.S. Patent No. 6,473,527 |
| 2000-01-21 | Priority Date for U.S. Patent Nos. 6,972,790 & 8,537,242 |
| 2002-10-29 | U.S. Patent No. 6,473,527 Issues |
| 2005-12-06 | U.S. Patent No. 6,972,790 Issues |
| 2013-09-17 | U.S. Patent No. 8,537,242 Issues |
| 2022-08-17 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,473,527 - "Module and method for interfacing analog/digital converting means and JPEG compression means," Issued Oct. 29, 2002
The Invention Explained
- Problem Addressed: The patent describes that conventional systems for JPEG image compression required an extra memory component (e.g., a RAM chip) to act as a buffer between the analog-to-digital (A/D) converter and the JPEG compression hardware. This extra memory was needed to re-format image data from a line-by-line stream into the 8x8 pixel blocks required by the JPEG algorithm, adding cost and complexity to devices like scanners. (’527 Patent, col. 1:44-57).
- The Patented Solution: The invention proposes an interface module that eliminates the need for this extra memory. A "read control device" reads a specific number of image lines (e.g., eight) from the A/D converter into a smaller, internal memory device. Once this memory holds enough data to form a compression block, an "output control device" sends the data as a correctly-sized block directly to the JPEG compression device. (’527 Patent, Abstract; col. 2:49-56).
- Technical Importance: This approach aimed to reduce the component count, cost, and complexity of digital imaging devices by enabling more direct communication between the image capture and compression stages. (’527 Patent, col. 2:21-23).
Key Claims at a Glance
- The complaint does not specify which claims are asserted, instead referring to "Exemplary '527 Patent Claims" in an external exhibit (Compl. ¶13, ¶15). Analysis of independent claim 1 provides a representative view of the technology.
- Independent Claim 1 requires:
- A "read control means" for sequentially reading a predetermined number of image lines from an A/D converter and generating a control signal.
- A "memory means" coupled to the read control means for storing those image lines, with a capacity equal to the built-in memory of the JPEG compression means.
- An "output control means" that responds to the control signal by sequentially reading an image block from the memory means and forwarding it to the JPEG compression means.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 6,972,790 - "Host interface for imaging arrays," Issued Dec. 6, 2005
The Invention Explained
- Problem Addressed: The patent notes that CMOS image sensors typically produce a "video style output" at a fixed rate, which is incompatible with the data interfaces of general-purpose microprocessors. This mismatch requires additional "glue logic" to bridge the two systems, undermining the cost and integration benefits of CMOS technology. (’790 Patent, col. 1:37-56).
- The Patented Solution: The invention describes an interface, preferably integrated on the same die as the image sensor, that decouples the sensor's data rate from the processor's. The interface uses a memory (such as a first-in-first-out, or FIFO, buffer) to store image data as it arrives from the sensor. A signal generator then alerts the host processor (e.g., via an interrupt) "in response to the quantity of data in the memory," allowing the processor to read the data from the buffer at its own pace. (’790 Patent, Abstract; col. 2:3-13).
- Technical Importance: This architecture is a key enabler for "System on a Chip" (SoC) designs, where an image sensor and its control logic can be integrated onto a single piece of silicon, leading to smaller, more power-efficient, and less expensive digital cameras and other imaging devices. (’790 Patent, col. 2:25-30).
Key Claims at a Glance
- The complaint does not specify which claims are asserted, instead referring to "Exemplary '790 Patent Claims" in an external exhibit (Compl. ¶19, ¶24). Analysis of independent claim 1 is representative.
- Independent Claim 1 requires:
- A "memory" for storing imaging array data and clocking signals at a rate determined by those signals.
- A "signal generator" for generating a signal for the processor system "in response to the quantity of data in the memory".
- A "circuit" for controlling the transfer of data from the memory at a rate determined by the processor system.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 8,537,242 - "Host interface for imaging arrays," Issued Sep. 17, 2013
Technology Synopsis
As a divisional of the ’790 Patent, the ’242 Patent covers similar technology. It describes an interface integrated with an image sensor for managing data transfer to a host processor. The interface uses a memory buffer and generates a signal, such as a bus request to a bus arbitration unit, based on the amount of data stored in the buffer, allowing the processor to control the final data transfer. (’242 Patent, Abstract; col. 2:2-20).
Asserted Claims
The complaint refers to "Exemplary '242 Patent Claims" in an external exhibit but does not identify them in the complaint body (Compl. ¶28, ¶33).
Accused Features
The complaint alleges that "Exemplary Defendant Products" infringe the patent by practicing the claimed technology but does not identify specific products or features in the complaint body (Compl. ¶28).
III. The Accused Instrumentality
Product Identification
- The complaint does not identify any specific accused products by name. It refers generally to "Exemplary Defendant Products" that are purportedly identified in external claim chart exhibits which are not attached to the filed complaint (Compl. ¶13, ¶19, ¶28).
Functionality and Market Context
- The complaint does not provide sufficient detail for analysis of the accused products' functionality or market context. It alleges that Defendant makes, uses, sells, and imports these unspecified products in the United States (Compl. ¶13, ¶19, ¶28).
No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint does not contain a narrative infringement theory or element-by-element analysis for any patent. Instead, it incorporates by reference external exhibits (Exhibits 4, 5, and 6) that allegedly contain claim charts (Compl. ¶16, ¶25, ¶34). As these exhibits were not provided with the complaint, the following charts outline the claim elements and cite the complaint's general allegation of infringement for each.
U.S. Patent No. 6,473,527 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| read control means coupled to said analog/digital converting means for sequentially reading a predetermined number of image lines from a data output of said analog/digital converting means, and generating a control signal... | The complaint alleges the "Exemplary Defendant Products" contain this functionality, incorporating by reference a claim chart in Exhibit 4. | ¶15 | col. 4:56-61 |
| memory means coupled to said read control means for storing said predetermined number of image lines, said memory means capable of storing the same number of image lines as said built-in memory device | The complaint alleges the "Exemplary Defendant Products" contain this functionality, incorporating by reference a claim chart in Exhibit 4. | ¶15 | col. 4:3-7 |
| and output control means in response to said control signal for sequentially reading an image block from said memory means and forwarding said image block to said built-in memory device. | The complaint alleges the "Exemplary Defendant Products" contain this functionality, incorporating by reference a claim chart in Exhibit 4. | ¶15 | col. 4:8-11 |
Identified Points of Contention
- Scope Questions: A central issue for the "means" limitations will be identifying the corresponding structure in the patent's specification and determining whether the accused products contain an identical or equivalent structure. For example, the court will need to determine the scope of the disclosed algorithm for the "read control means".
- Technical Questions: A factual question may be whether the accused products' memory management system functions as claimed, specifically by reading a predetermined number of lines and then forwarding distinct image blocks to a compression device, as opposed to using a more generic data buffering scheme.
U.S. Patent No. 6,972,790 Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a memory for storing imaging array data and clocking signals at a rate determined by the clocking signals | The complaint alleges the "Exemplary Defendant Products" contain this functionality, incorporating by reference a claim chart in Exhibit 5. | ¶24 | col. 8:8-11 |
| a signal generator for generating a signal for transmission to the processor system in response to the quantity of data in the memory | The complaint alleges the "Exemplary Defendant Products" contain this functionality, incorporating by reference a claim chart in Exhibit 5. | ¶24 | col. 8:12-15 |
| and a circuit for controlling the transfer of the data from the memory at a rate determined by the processor system. | The complaint alleges the "Exemplary Defendant Products" contain this functionality, incorporating by reference a claim chart in Exhibit 5. | ¶24 | col. 8:16-18 |
Identified Points of Contention
- Scope Questions: The phrase "in response to the quantity of data in the memory" may become a critical point of claim construction. The dispute could center on whether this requires the specific disclosed embodiment of comparing a data counter to a pre-set limit (’790 Patent, col. 6:11-15), or if it can read more broadly on any system where the processor is signaled based on the memory's state.
- Technical Questions: An evidentiary question will be what event or logic actually triggers the data transfer signal in the accused products. The analysis will investigate whether the signal is truly generated based on the quantity of data in a buffer, or if it is triggered by other events, such as the completion of a full image frame capture.
V. Key Claim Terms for Construction
For the ’527 Patent:
- The Term: "read control means"
- Context and Importance: This is a means-plus-function limitation under 35 U.S.C. § 112(f). Its scope is limited to the corresponding structure disclosed in the specification and its equivalents. The viability of Plaintiff's infringement case will depend heavily on whether the architecture of the accused products is structurally equivalent to the specific algorithm and hardware disclosed in the patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language recites the function broadly as "sequentially reading a predetermined number of image lines... and generating a control signal" (’527 Patent, col. 4:57-61).
- Evidence for a Narrower Interpretation: The specification discloses a specific corresponding structure: the "read control device 22" (’527 Patent, Fig. 2) which operates according to a specific flowchart. This includes steps like initializing counters, reading data line-by-line until a counter "I" equals a predetermined number "N", and then proceeding to a compression decision step (’527 Patent, Fig. 3, steps 301-304). A defendant would likely argue the claim is limited to this disclosed algorithmic structure.
For the ’790 Patent:
- The Term: "in response to the quantity of data in the memory"
- Context and Importance: This term defines the trigger for communication between the imaging interface and the host processor. Practitioners may focus on this term because it distinguishes the invention from systems that might transfer data based on a fixed schedule or other triggers unrelated to the buffer's fill level. The infringement analysis will turn on the causal link between the amount of stored data and the generation of the signal.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The plain language of the claim suggests any causal relationship where the signal is generated because of the amount of data in memory, regardless of the specific mechanism.
- Evidence for a Narrower Interpretation: The detailed description discloses a specific embodiment where an "interrupt generator 48" "compares the FIFO counter output Sc and the FIFO limit SL" and asserts an interrupt signal "if Sc >= SL" (’790 Patent, col. 6:11-15). A defendant may argue that this disclosed comparison logic limits the scope of the claim term.
VI. Other Allegations
- Indirect Infringement: For the ’790 and ’242 patents, the complaint alleges induced infringement. The factual basis asserted is that Defendant distributes "product literature and website materials" that allegedly instruct end users to operate the accused products in an infringing manner (Compl. ¶22, ¶31).
- Willful Infringement: For the ’790 and ’242 patents, the complaint alleges willfulness based on post-suit knowledge. It asserts that the filing of the complaint provided Defendant with "actual knowledge of infringement" and that Defendant's continued infringement thereafter is willful (Compl. ¶21-22, ¶30-31). No allegations of pre-suit knowledge are made.
VII. Analyst’s Conclusion: Key Questions for the Case
A threshold procedural issue will be one of pleading sufficiency: does the complaint's exclusive reliance on incorporating external, unattached exhibits, without providing any substantive factual allegations in the body of the complaint to identify the accused products or the mechanism of infringement, meet the plausibility standard required by federal pleading rules?
For the ’527 Patent, the case will likely involve a core question of structural equivalence: are the means-plus-function claim limitations, which are tied to a specific algorithms and structures disclosed in the patent, broad enough to read on the potentially more modern and varied memory-management architectures in the accused products?
For the ’790 and ’242 Patents, a central dispute will be one of definitional scope: can the phrase "in response to the quantity of data," which is described in the patent as a specific counter-and-limit comparison, be construed to cover other asynchronous data-transfer triggers that may be used in the accused systems? This will determine whether there is a fundamental match or mismatch in technical operation.