North Plate Semiconductor LLC v. Microchip Technology Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: North Plate Semiconductor, LLC (Delaware)
  • Defendant: Microchip Technology Inc. (Delaware); Microsemi Corporation (Delaware)
  • Plaintiff’s Counsel: Kroub, Silbersher & Kolmykov PLLC
• Case Identification: 2:18-cv-07128, E.D.N.Y., 12/14/2018
• Venue Allegations: Venue is alleged to be proper in the Eastern District of New York based on Defendants' commission of infringing acts within the district and Defendant Microchip Technology's maintenance of a regular and established place of business in Hauppauge, New York.
• Core Dispute: Plaintiff alleges that Defendants’ Insulated Gate Bipolar Transistor (IGBT) semiconductor devices infringe two patents related to the physical structure and manufacturing methods for high-voltage power transistors.
• Technical Context: The patents relate to IGBTs, which are high-power semiconductor switches essential for power electronics in diverse markets including electric vehicles, industrial controls, and communications infrastructure.
• Key Procedural History: The complaint alleges that Defendants received notice of infringement for both patents-in-suit via letters and subsequent communications beginning on or about January 22, 2018, nearly eleven months prior to the complaint's filing. The complaint also notes that Defendant Microchip Technology completed its acquisition of Defendant Microsemi Corporation on May 29, 2018.

Case Timeline

Date	Event
2000-09-28	U.S. Patent No. 6,620,653 Priority Date
2001-01-31	U.S. Patent No. 6,617,641 Priority Date
2003-09-09	U.S. Patent No. 6,617,641 Issues
2003-09-16	U.S. Patent No. 6,620,653 Issues
2018-01-22	Alleged date of first pre-suit notice of infringement
2018-05-29	Microchip Technology completes acquisition of Microsemi
2018-06-02	Alleged date of second pre-suit notice letter
2018-12-14	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,617,641 - "High Voltage Semiconductor Device Capable of Increasing a Switching Speed," Issued Sep. 9, 2003

The Invention Explained

• Problem Addressed: The patent describes two problems with conventional "punch-through" IGBTs. First, techniques to increase switching speed often undesirably increase the device's ON-voltage. Second, when the device is turned off, the current drops to zero very rapidly, which can cause voltage oscillation and electronic noise (’641 Patent, col. 2:1-24).
• The Patented Solution: The invention introduces a "low concentration layer" between the device's drain layer and buffer layer (’641 Patent, col. 2:32-41). This additional layer is designed to allow charge carriers to accumulate and then dissipate more gradually when the device is switched off. This gradual decrease in current is intended to prevent the voltage oscillations and noise associated with abrupt turn-offs, while also improving the trade-off between switching speed and ON-voltage (’641 Patent, col. 5:11-28).
• Technical Importance: The invention purports to solve a fundamental performance limitation in high-speed, high-voltage power switching devices by mitigating noise and improving efficiency.

Key Claims at a Glance

• The complaint asserts infringement of claims 1-10 (Compl. ¶30). Independent claim 1 is representative and requires:
  • A drain layer of a first conductivity type;
  • A buffer layer of a second conductivity type formed above the drain layer;
  • A high resistance layer of the second conductivity type formed on the buffer layer;
  • A base layer of the first conductivity type formed on the high resistance layer;
  • A source layer of the second conductivity type in a surface region of the base layer;
  • A gate electrode formed at the base layer with an insulating film;
  • A low concentration layer formed between the drain and buffer layers, with an impurity concentration lower than both; and
  • Wherein the drain layer is an impurity diffusion layer with a total impurity amount at most 5x10¹⁴ cm⁻².

U.S. Patent No. 6,620,653 - "Semiconductor Device and Method of Manufacturing the Same," Issued Sep. 16, 2003

The Invention Explained

• Problem Addressed: The patent identifies the high manufacturing cost of conventional IGBTs, which often rely on expensive epitaxial substrates, as a key problem. It also notes the persistent engineering trade-off between a device’s turn-off characteristics and its on-state characteristics (’653 Patent, col. 1:11-19, 1:55-65).
• The Patented Solution: The invention describes a semiconductor device structure, and a method for making it, that avoids using an epitaxial substrate. Instead, it relies on ion-implantation to form the necessary layers on a standard semiconductor substrate (’653 Patent, col. 4:10-15). A core feature is a "low injection efficiency emitter structure," achieved by using a thin collector layer with a low dose of impurities. This structure is designed to enable fast turn-off speeds without requiring "life time control," a separate process that can degrade other performance characteristics. The desired performance is defined by a specific mathematical relationship between the properties of the buffer and collector layers (’653 Patent, col. 4:22-38).
• Technical Importance: The technology proposes a pathway to lower the manufacturing cost of high-voltage power devices while simultaneously improving the fundamental performance trade-offs.

Key Claims at a Glance

• The complaint asserts infringement of claims 10, 12, 13, and 14 (Compl. ¶41). Independent claim 10 is representative and requires:
  • A first base layer (semiconductor substrate);
  • A collector layer on a first surface of the base layer;
  • A buffer layer between the base layer and collector layer;
  • A second base layer on a second surface of the base layer;
  • An emitter layer in the second base layer;
  • A gate electrode above the second base layer; and
  • Wherein the device satisfies the condition: 5 ≥ bDP·QP/bDN·QN, a formula relating the dose amounts (QP, QN) and average diffusion coefficients (bDP, bDN) of the collector and buffer layers.

III. The Accused Instrumentality

Product Identification

• The complaint identifies "at least Microsemi's IGBT Power MOS 8 with PT and IGBT Power MOS 7 with PT devices" as the Accused Products (Compl. ¶26).

Functionality and Market Context

• The Accused Products are described as Insulated Gate Bipolar Transistors (IGBTs) that use "PT (punch through) technology" (Compl. ¶¶30, 41). The complaint alleges these components are designed for and used in a wide array of high-value markets, including "medical imaging, powertrain & EV charging, communications infrastructure systems, ... military and commercial satellites and aircraft, and enterprise storage and hyperscale data centers" (Compl. ¶26).

IV. Analysis of Infringement Allegations

No probative visual evidence provided in complaint.

’641 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a drain layer of a first conductivity type	The complaint alleges, on information and belief, that because the Accused Products are IGBTs, they contain the claimed drain layer (Compl. ¶30).	¶30	col. 3:35-40
a buffer layer of a second conductivity type formed above the drain layer	The complaint alleges that because the Accused Products use "PT (punch through) technology," they contain the claimed buffer layer, and that this layer is a different conductivity type from the drain layer (Compl. ¶30).	¶30	col. 3:37-38
a high resistance layer... a base layer... a source layer... a gate electrode...	The complaint alleges on information and belief that the Accused Products, as IGBT devices, contain these standard structural layers (Compl. ¶30).	¶30	col. 3:42-54
a low concentration layer formed between the drain layer and the buffer layer, an impurity concentration of the low concentration layer being lower than those of the drain layer...	The complaint does not specifically allege the presence of this layer, but states that "The remaining elements of claims 1-10 are alleged upon information and belief" (Compl. ¶30).	¶30	col. 3:37-40
wherein the drain layer is an impurity diffusion layer, and a total amount of impurities contained in the drain layer is at most 5x10¹⁴ cm⁻²	The complaint does not provide specific facts to support this quantitative limitation, instead relying on a general allegation that the remaining claim elements are met (Compl. ¶30).	¶30	col. 3:23-26

• Identified Points of Contention:
  • Structural Questions: The complaint's allegations are conclusory, inferring the presence of claimed layers from the fact that the accused devices are "IGBTs." A primary question will be whether the Plaintiff can produce technical evidence (e.g., from circuit analysis or device cross-sectioning) demonstrating that the accused devices actually possess the specific seven-layer structure of claim 1, most notably the distinct "low concentration layer" positioned between the drain and buffer layers.
  • Quantitative Questions: The infringement case will require evidence that the accused devices meet the quantitative impurity limit for the drain layer. The complaint provides no factual basis for this allegation, raising the question of what evidence, if any, supports this element of the claim.

’653 Patent Infringement Allegations

Claim Element (from Independent Claim 10)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
a first conductive type first base layer; a second conductive type collector layer... a first conductive type buffer layer... a second conductive type second base layer... an emitter layer... a gate electrode...	The complaint alleges on information and belief that because the Accused Products are IGBTs that use "PT (punch through) technology," they contain these claimed structural layers (Compl. ¶41).	¶41	col. 4:10-14
wherein the following condition is satisfied: 5 ≥ bDP·QP/bDN·QN	The complaint makes no factual allegation to support this mathematical limitation. It states that "The remaining elements of claims 10, 12, 13 and 14 are alleged upon information and belief" after listing only the structural layers (Compl. ¶41).	¶41	col. 13:16-22

• Identified Points of Contention:
  • Evidentiary Questions: The complaint provides no factual allegations to support the core mathematical limitation of claim 10. The central technical and evidentiary question for this patent will be whether Plaintiff can prove, through testing and analysis of the accused devices, that their physical properties satisfy this specific formula. The absence of any supporting facts in the complaint suggests this will be a primary focus of discovery and dispositive motions.

V. Key Claim Terms for Construction

’641 Patent: "low concentration layer"

• Context and Importance: This term describes the central inventive concept of the '641 patent. The existence, structure, and properties of this specific layer will be critical to the infringement analysis. Practitioners may focus on this term because its alleged presence distinguishes the patented invention from conventional IGBTs.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: Claim 1 defines the term functionally and relatively, requiring only that it be "formed between the drain layer and the buffer layer" and have an "impurity concentration ... lower than those of the drain layer and the buffer layer" (’641 Patent, col. 9:15-19).
  • Evidence for a Narrower Interpretation: The specification describes the layer's function as enabling a gradual current reduction to prevent noise (’641 Patent, col. 5:11-28) and provides specific exemplary thicknesses (0.5 to 30 µm) and impurity concentrations (e.g., 1x10¹⁶ cm⁻³) (’641 Patent, col. 3:61-64). A party could argue that these embodiments and functional descriptions limit the scope of the term.

’653 Patent: "wherein the following condition is satisfied: 5 ≥ bDP·QP/bDN·QN"

• Context and Importance: This quantitative formula is a dispositive limitation in independent claim 10. Infringement cannot be found unless this mathematical condition is met. Practitioners may focus on this term because it presents a high and very specific evidentiary bar for the plaintiff.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: A party may argue that the terms within the formula—dose amount (Q) and average diffusion coefficient (b)—are standard, well-understood parameters in semiconductor physics, making the formula a straightforward calculation based on measurable device properties.
  • Evidence for a Narrower Interpretation: The patent explains how these values are derived, for instance, by integrating a concentration profile over the thickness of a layer to find the dose amount (’653 Patent, col. 13:30-49). A party could argue that the term is indefinite if the method for measuring these values (e.g., defining the exact boundaries of the "buffer layer" for integration) is not sufficiently clear, or that the interpretation must be constrained by the specific examples and simulation results discussed in the specification.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement of infringement based on Defendants providing "datasheets, application notes, product briefs, and other collateral" on their website, which allegedly encourage and instruct customers and distributors on how to use the accused products in an infringing manner (Compl. ¶¶31-32, 42-43).
• Willful Infringement: The complaint alleges willful infringement based on Defendants' alleged knowledge of the patents since at least January 22, 2018, as a result of pre-suit notice letters and subsequent communications between the parties (Compl. ¶¶34-35, 45-46).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of structural proof: Can the plaintiff produce technical evidence to demonstrate that the physical, layered structure of the accused IGBTs contains the distinct "low concentration layer" as required by the ’641 patent, or will discovery reveal a different structure that achieves a similar result through un-claimed means?
2. A key evidentiary hurdle will be one of quantitative satisfaction: Does Plaintiff possess, or can it develop, evidence to prove that the accused devices meet the specific mathematical formula ("5 ≥ bDP·QP/bDN·QN") required by the ’653 patent? The complaint's complete lack of factual allegations on this point raises this as a critical question for the viability of the infringement claim on this patent.
3. The outcome may also depend on definitional clarity: The litigation will likely involve disputes over how to construe and measure the properties of the claimed layers, particularly the "low concentration layer" in the ’641 patent and the variables (dose amount, average diffusion coefficient) used in the ’653 patent’s infringement formula.