Altair Logix LLC v. Exor Electronic Research Development Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Altair Logix LLC (Texas)
  • Defendant: Exor Electronic Research and Development, Inc. (Ohio)
  • Plaintiff’s Counsel: Sand, Sebolt & Wernow Co., LPA; Direction IP Law
• Case Identification: 1:21-cv-00128, S.D. Ohio, 02/23/2021
• Venue Allegations: Venue is alleged to be proper because Defendant is an Ohio corporation that resides in the district and has committed acts of infringement within the district.
• Core Dispute: Plaintiff alleges that Defendant’s eX700 Series of industrial controllers, which incorporate ARM multi-core processors, infringe a patent directed to a dynamically reconfigurable system-on-a-chip architecture.
• Technical Context: The technology relates to reconfigurable computing architectures for systems-on-a-chip (SoCs), which seek to combine the performance of fixed-function hardware with the flexibility of programmable software for demanding media processing applications.
• Key Procedural History: The complaint notes that the asserted independent claim of the patent-in-suit was an originally filed claim that issued without amendment or rejection based on prior art, which may be raised by the plaintiff to argue for a strong presumption of validity.

Case Timeline

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 6,289,434 - "Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates," Issued September 11, 2001

The Invention Explained

• Problem Addressed: The patent describes the trade-offs in then-existing integrated circuit design. Hard-wired, fixed-function circuits offered high performance but were inflexible and costly due to "temporal redundancy," where specialized silicon remains idle when not in use. Conversely, programmable solutions like general-purpose microprocessors, DSPs, and FPGAs lacked the performance or cost-effectiveness for complex, real-time tasks like 3D graphics or video processing (Compl. ¶¶13-19; ’434 Patent, col. 1:40-2:63).
• The Patented Solution: The invention proposes a novel apparatus for implementing systems on a chip that aims to achieve the performance of fixed-function hardware at a lower cost by using a dynamically reconfigurable architecture. The core of the solution is a plurality of "media processing units" that can be reconfigured in run-time to adapt to varying data and processing requirements, thereby reducing redundancy by re-using computational elements (Compl. ¶20; ’434 Patent, col. 2:64-3:8). This dynamic reconfiguration is a key aspect, allowing the circuit to adapt "on the fly" without performance degradation (Compl. ¶20; ’434 Patent, col. 3:8-11). Figure 3 of the patent illustrates an embodiment with eight media processing units interconnected on-chip (Compl. ¶23; ’434 Patent, Fig. 3).
• Technical Importance: The invention addresses the enduring challenge in semiconductor design of balancing performance, cost, and flexibility, proposing a parallel, reconfigurable architecture for the growing class of media-intensive applications (Compl. ¶12; ’434 Patent, col. 1:32-38).

Key Claims at a Glance

• The complaint asserts independent claim 1 and reserves the right to assert other claims (Compl. ¶26; Compl. ¶41.a).
• The essential elements of independent claim 1 are:
  • An apparatus for processing data, comprising:
  • An addressable memory for storing data and instructions, with input/outputs;
  • A plurality of media processing units, each coupled to the memory and comprising: a multiplier, an arithmetic unit, an arithmetic logic unit (ALU), and a bit manipulation unit;
  • The ALU must be capable of operating concurrently with the multiplier and/or the arithmetic unit;
  • The bit manipulation unit must be capable of operating concurrently with the ALU and at least the multiplier or the arithmetic unit;
  • Each of the plurality of media processing units must be capable of performing an operation simultaneously with other media processing units;
  • The operation itself comprises receiving an instruction and data from memory, processing the data to produce a result, and providing the result at the unit's input/output.

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are Defendant’s eX700 Series of "Revolutionary IIoT Controllers," including at least models eX712, eX707, and eX710 (Compl. ¶26). A product lineup image from the Defendant's website shows the various models (Compl. ¶27, p. 10).

Functionality and Market Context

The products are marketed as high-performance, all-in-one industrial controllers featuring multi-touch screens and integrated PLCs (Compl. ¶27). The complaint alleges that the technical basis for the infringement lies in the products' use of multi-core ARM Cortex-A9 processors (Compl. ¶28). Specifically, the complaint identifies the dual or quad ARM cores as the claimed "plurality of media processing units" and alleges that the NEON media coprocessor integrated within each core contains the claimed multiplier, arithmetic unit, ALU, and bit manipulation unit (Compl. ¶¶28-32).

IV. Analysis of Infringement Allegations

'434 Patent Infringement Allegations

Identified Points of Contention

• Scope Questions: A central dispute may arise over whether a standard, off-the-shelf ARM Cortex-A9 processor can be considered a "media processing unit" as defined by the patent. The patent heavily emphasizes its architecture's "dynamic-adaptive run-time reconfigurable" nature, which may be argued to distinguish it from a general-purpose processor with a fixed microarchitecture. The question for the court will be whether the definition is primarily structural (requiring the specific reconfigurability described) or functional (requiring only the presence of the listed sub-units).
• Technical Questions: The complaint alleges that the various sub-units of the NEON coprocessor meet the specific concurrency requirements of claim 1. For example, it must be proven that the "bit manipulation unit" is capable of operating concurrently with both the "arithmetic logic unit" and at least one of the "multiplier" or "arithmetic unit." The complaint asserts this capability by referencing high-level block diagrams, but the actual operational concurrency of the processor's internal pipeline will be a key technical question requiring detailed evidence.

V. Key Claim Terms for Construction

The Term: "media processing unit"

Context and Importance

This term defines the core building block of the claimed apparatus. The viability of the infringement case depends on this term being construed to cover the ARM Cortex-A9 processor cores in the accused products. Practitioners may focus on this term because its construction will likely determine whether the patent applies to standard off-the-shelf processors or is limited to the specific custom, reconfigurable architecture described in the specification.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The patent claims the unit in terms of its constituent components (multiplier, arithmetic unit, etc.) and their interconnections, without explicitly requiring "reconfigurability" in the language of claim 1 itself (’434 Patent, col. 55:31-56:20). A party could argue that any processor containing these functional blocks meets the definition.
• Evidence for a Narrower Interpretation: The specification repeatedly describes the invention as an "apparatus for adaptively dynamically reconfiguring groups of computations and storage elements in run-time" (’434 Patent, col. 3:14-16) and refers to the aggregate of these elements as a "media processing unit" (Compl. ¶21). A party could argue that this dynamic reconfigurability is a defining characteristic of the "media processing unit" and is not a feature of a standard ARM processor.

The Term: "capable of operating concurrently with"

Context and Importance

This phrase appears in two separate limitations with different requirements, governing the operational relationship between the ALU, bit manipulation unit, multiplier, and arithmetic unit. Proving infringement requires showing the accused processor has these specific concurrent capabilities.

Intrinsic Evidence for Interpretation

• Evidence for a Broader Interpretation: The patent does not provide a special definition for "concurrently," suggesting it should be given its plain meaning. A party may argue that modern pipelined and superscalar processor architectures, which execute different stages of multiple instructions at the same time, inherently possess this capability. The block diagrams in the complaint appear to support this view by showing parallel execution pipelines (Compl. p. 14).
• Evidence for a Narrower Interpretation: A party could argue that the claim requires a specific combination of simultaneous operations that is distinct from standard pipelining. For example, the bit manipulation unit must be capable of operating concurrently with the ALU and also the multiplier or arithmetic unit (’434 Patent, col. 55:47-53). A factual dispute may arise over whether the accused ARM architecture can perform this specific multi-part concurrent operation as claimed.

VI. Other Allegations

The complaint does not provide sufficient detail for analysis of indirect or willful infringement.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "media processing unit," rooted in the patent’s description of a custom, "dynamic-adaptive run-time reconfigurable" architecture, be construed to cover a standard, off-the-shelf ARM processor core? The outcome may hinge on whether the claim is interpreted functionally, based on the presence of certain sub-components, or structurally, requiring the specific reconfigurability detailed in the specification.
• A key evidentiary question will be one of technical mapping: does the accused ARM Cortex-A9 processor, and specifically its NEON coprocessor, actually possess the precise, multi-part concurrency capabilities recited in claim 1? The plaintiff will need to provide detailed technical evidence beyond high-level block diagrams to prove that the accused device's "bit manipulation unit" can operate concurrently with its "arithmetic logic unit" and at least one other specified unit, as the claim language demands.