DCT
3:22-cv-01282
Bell Semiconductor LLC v. Lattice Semiconductor Corp
Key Events
Amended Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Lattice Semiconductor Corp. (Oregon)
- Plaintiff’s Counsel: Pitzer Law; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: Bell Semiconductor, LLC v. Lattice Semiconductor Corp., 3:22-cv-01282, D. Or., 11/03/2022
- Venue Allegations: Venue is alleged to be proper in the District of Oregon because Defendant maintains its principal place of business and corporate headquarters in Hillsboro, Oregon, and allegedly commits acts of infringement, employs relevant personnel, and derives substantial revenue within the district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor design and validation processes infringe two patents related to improving the efficiency of electronic design automation (EDA) by enabling early-stage error detection and incremental updates to circuit layouts.
- Technical Context: The technology concerns software methods used in the design of complex integrated circuits, specifically addressing bottlenecks in the validation and manufacturing-preparation stages of the design flow.
- Key Procedural History: The complaint is a First Amended Complaint. Plaintiff Bell Semiconductor is presented as a successor to Bell Labs, holding a large portfolio of semiconductor-related patents. No prior litigation between the parties or administrative proceedings concerning the patents-in-suit are mentioned.
Case Timeline
| Date | Event |
|---|---|
| 2003-10-10 | U.S. Patent No. 7,260,803 Priority Date |
| 2004-09-22 | U.S. Patent No. 7,149,989 Priority Date |
| 2006-12-12 | U.S. Patent No. 7,149,989 Issued |
| 2007-08-21 | U.S. Patent No. 7,260,803 Issued |
| 2022-11-03 | First Amended Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,149,989 - “Method of Early Physical Design Validation and Identification of Texted Metal Short Circuits in an Integrated Circuit Design”
- Issued: December 12, 2006 (the “'989 Patent”)
The Invention Explained
- Problem Addressed: The patent’s background section describes the dilemma in semiconductor design validation: running a full validation check late in the process is risky, as a detected fault could force a costly and time-consuming restart of the entire design cycle. Conversely, running a full check early on an incomplete design generates a large number of false-positive errors, making it difficult to identify genuine problems. (’989 Patent, col. 2:40-58; Compl. ¶25).
- The Patented Solution: The invention proposes a method for targeted, early-stage validation. It involves generating a "specific rule deck" from a comprehensive physical design rule deck. This new, smaller deck contains only the rules necessary to check for a specific class of critical errors—"texted metal short circuits" between different power, ground, and signal sources. By using this focused rule set, designers can efficiently find critical faults early without the noise of a full validation. (’989 Patent, Abstract; col. 2:64-3:3).
- Technical Importance: This selective validation approach allows for the early detection and correction of significant design flaws, which reduces computer processing time, avoids major redesigns, and shortens the overall product development timeline. (’989 Patent, col. 3:7-11; Compl. ¶8).
Key Claims at a Glance
- The complaint asserts independent claim 1. (Compl. ¶27).
- The essential elements of claim 1 are:
- Receiving a representation of an integrated circuit design.
- Receiving a physical design rule deck specifying rule checks.
- Generating a "specific rule deck" from the physical design rule deck that includes only rules specific to "texted metal short circuits" between different signal sources, power, and ground.
- Performing a physical design validation on the design using the "specific rule deck" to identify those short circuits.
- The complaint alleges infringement of "one or more claims," which may suggest an intent to assert dependent claims as the case develops. (Compl. ¶43).
U.S. Patent No. 7,260,803 - “Incremental Dummy Metal Insertions”
- Issued: August 21, 2007 (the “'803 Patent”)
The Invention Explained
- Problem Addressed: In semiconductor manufacturing, "dummy fill" (non-functional metal) is added to a design to ensure uniform surface density for Chemical Mechanical Polishing (CMP). The patent notes that if a design change is required late in the process, the conventional method requires discarding all the previously calculated dummy fill and re-running the entire, time-consuming (e.g., up to 30 hours) dummy fill software tool from scratch. (’803 Patent, col. 1:51-65; Compl. ¶34).
- The Patented Solution: The patent describes an "incremental" update method. After a design change (an Engineering Change Order, or ECO), the process does not start over. Instead, it performs a check to see if any of the existing dummy metal objects now intersect with any other design objects. If an intersection is found, only the specific, intersecting dummy metal object is deleted, leaving the rest of the valid dummy fill intact and avoiding a full rerun of the tool. (’803 Patent, Abstract; col. 2:6-14).
- Technical Importance: This invention saves significant time and cost when making late-stage design modifications, thereby increasing design flexibility and helping manufacturers meet aggressive production schedules. (’803 Patent, col. 2:20-23; Compl. ¶5).
Key Claims at a Glance
- The complaint asserts independent claim 1. (Compl. ¶36).
- The essential elements of claim 1 are:
- Starting with design data for an integrated circuit that already includes dummy metal objects inserted by a dummy fill tool.
- After a portion of the design data is changed, performing a check to determine if any dummy metal objects intersect with any other objects in the design data.
- Deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool.
- The complaint alleges infringement of "one or more claims," suggesting dependent claims may also be at issue. (Compl. ¶56).
III. The Accused Instrumentality
Product Identification
The complaint accuses Lattice’s internal "Accused Processes"—its methodologies for designing and validating semiconductor devices using EDA tools from vendors like Cadence, Synopsys, and/or Siemens. (Compl. ¶¶44, 57). The Lattice LCMX02-7000HC semiconductor device is identified as one example product designed and manufactured using these allegedly infringing processes. (Compl. ¶¶43, 56).
Functionality and Market Context
The complaint alleges that Lattice’s design processes incorporate the patented technologies to improve efficiency. For the ’989 Patent, the Accused Processes are alleged to use a "short finder" or "short locator" functionality to perform early-stage validation for metal short circuits. (Compl. ¶46). For the ’803 Patent, the Accused Processes are alleged to employ a Design Rule Check ("DRC") tool after an Engineering Change Order ("ECO") to identify and "delete" or "trim" dummy fill geometries that intersect with other design objects. (Compl. ¶¶58-59). The complaint asserts these process efficiencies provide significant commercial value and competitive advantages to Lattice. (Compl. ¶¶5, 8).
No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
’989 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input a representation of an integrated circuit design; | Lattice's Accused Processes import a circuit design, such as for the LCMX02-7000HC, into an EDA tool (e.g., from Cadence, Synopsys, or Siemens). | ¶44 | col. 1:31-33 |
| (b) receiving as input a physical design rule deck that specifies rule checks to be performed on the integrated circuit design; | The EDA tool used by Lattice allegedly receives various in-design verification processes for concurrent physical design and verification. | ¶45 | col. 1:34-36 |
| (c) generating a specific rule deck from the physical design rule deck wherein the specific rule deck includes only physical design rules that are specific to texted metal short circuits...; and | The Accused Processes employ a design tool with a "short finder" or "short locator" functionality that identifies texted metal short circuits between different signal sources, including power and ground. | ¶46 | col. 1:37-43 |
| (d) performing a physical design validation on the integrated circuit design from the specific rule deck to identify texted metal short circuits between different signal sources... in the integrated circuit design. | The Accused Processes perform validation using the "short finder" functionality to identify the specified short circuits, which allegedly allows designers to select and view them by properties like cell, text, and net. | ¶46 | col. 1:44-47 |
’803 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method for performing dummy metal insertion in design data for an integrated circuit, which includes dummy metal objects inserted by a dummy fill tool... | Lattice's design processes for products like the LCMX02-7000HC include dummy metal objects inserted by a dummy fill tool as part of an "integrated" or "in-design" flow. | ¶57 | col. 1:32-41 |
| (a) after a portion of the design data is changed, performing a check to determine whether any dummy metal objects intersect with any other objects in the design data; and | After an ECO is received, Lattice allegedly employs a DRC tool to check for rule violations in the design data, including violations related to metal fill geometries intersecting with layout changes. | ¶58 | col. 2:10-12 |
| (b) deleting the intersecting dummy metal objects from the design data, thereby avoiding having to rerun the dummy fill tool. | The Accused Processes allegedly "delete the intersecting dummy metal objects" by using a tool that "repairs DRC violations" and allows designers to "trim metal fill geometries that cause the short." | ¶59 | col. 2:12-14 |
Identified Points of Contention
- Technical Questions: A primary question for the ’989 Patent infringement theory is whether the accused "short finder" functionality in a commercial EDA tool operates by "generating a specific rule deck" from a larger one, as claimed, or if it functions through a different mechanism, such as applying a pre-configured filter or a specialized, non-deck-based algorithm.
- Scope Questions: For the ’803 Patent, a potential point of dispute is the scope of the term "deleting." The complaint alleges that Lattice's tools "repair" violations and "trim" geometries. (Compl. ¶59). The court may need to determine if "trimming" a portion of an intersecting dummy object constitutes "deleting the intersecting dummy metal objects" as required by the claim, or if the claim requires removal of the entire object.
V. Key Claim Terms for Construction
Term:
generating a specific rule deck(’989 Patent, Claim 1)- Context and Importance: This term is central to the inventive concept of the ’989 Patent. The infringement case may depend on whether Lattice’s alleged use of a "short finder" feature in a third-party tool meets this limitation. Practitioners may focus on this term because the accused functionality is performed by general-purpose EDA tools, and the outcome will likely depend on whether their operation can be characterized as creating a new, subset rule deck.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states the invention provides "design rules that may be used in conjunction with a design rule check tool" (’989 Patent, col. 2:65-67), which a party could argue is broad enough to cover configuring or invoking a specific feature of an existing tool, rather than creating a wholly new file.
- Evidence for a Narrower Interpretation: The claim language "generating a specific rule deck from the physical design rule deck" and the flowchart in Figure 2, which depicts a "SPECIFIC DESIGN RULE DECK(S)" (214) as a discrete input to a "VALIDATION TOOL" (216), could support a narrower construction requiring the creation of a new, distinct data structure or file.
Term:
deleting the intersecting dummy metal objects(’803 Patent, Claim 1)- Context and Importance: This term defines the core action that provides the claimed efficiency gain. The complaint alleges that the accused processes "trim" and "repair" intersecting geometries (Compl. ¶59), raising the question of whether this action falls within the scope of "deleting."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A party might argue that "deleting" should be interpreted functionally to mean removing the portion of the object that causes the intersection, as this achieves the same goal of resolving the violation without rerunning the entire tool.
- Evidence for a Narrower Interpretation: The plain language suggests complete removal. The patent states, "the intersecting dummy metal objects are deleted from the design data" (’803 Patent, col. 2:12-14) and the flowchart in Figure 2 includes a step to "Delete the object" (114), which may imply removal of the entire object, not just modification.
VI. Other Allegations
Willful Infringement
The complaint alleges that Lattice's infringement is "exceptional" and entitles Plaintiff to attorneys' fees under 35 U.S.C. § 285. (Compl. ¶¶49, 62). However, it does not plead specific facts to support a claim for willful infringement, such as alleging that Lattice had pre-suit knowledge of the patents-in-suit.
VII. Analyst’s Conclusion: Key Questions for the Case
This case appears to center on the interpretation of key claim terms as applied to the functionality of sophisticated, off-the-shelf EDA software. The central questions for the court will likely be:
- A core issue will be one of technical and functional equivalence: Does the operation of a "short finder" feature within a commercial EDA tool constitute "generating a specific rule deck" as required by the ’989 Patent, or is there a fundamental mismatch in how the accused process and the claimed method operate?
- A second key issue will be one of definitional scope: Can the term
deleting, in the context of the ’803 Patent, be construed to cover the alleged acts of "trimming" or "repairing" an intersecting dummy metal object, or does the claim strictly require the complete removal of the object from the design data? - A significant evidentiary question will be what discovery reveals about Lattice's actual, internal design processes. The complaint's allegations are based on "information and belief" about how Lattice uses third-party tools; the viability of the infringement claims will depend on whether the evidence of Lattice's specific configurations and workflows supports the plaintiff's characterization.