DCT
3:22-cv-01435
Bell Semiconductor LLC v. Ampere Computing LLC
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Ampere Computing, LLC (California)
- Plaintiff’s Counsel: Pitzer Law; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 3:22-cv-01435, D. Or., 11/16/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Oregon because Defendant maintains a regular and established place of business in the district, advertises jobs there, and commits acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s methodologies for designing its semiconductor chips, such as the AC7-M128-30 Altra Max, infringe patents related to the strategic placement of "dummy metal" in integrated circuit layouts to improve manufacturability.
- Technical Context: The technology concerns methods for inserting non-functional "dummy fill" into semiconductor layouts to ensure uniform material density, a critical requirement for the chemical-mechanical polishing (CMP) process essential to modern chip fabrication.
- Key Procedural History: The complaint does not reference any prior litigation, licensing history, or post-grant proceedings for the patents-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2000-01-18 | U.S. Patent No. 6,436,807 Priority Date |
| 2002-08-20 | U.S. Patent No. 6,436,807 Issue Date |
| 2003-07-31 | U.S. Patent No. 7,007,259 Priority Date |
| 2006-02-28 | U.S. Patent No. 7,007,259 Issue Date |
| 2022-11-16 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,007,259 - "Method for Providing Clock-Net Aware Dummy Metal Using Dummy Regions"
The Invention Explained
- Problem Addressed: The patent describes that prior art methods for inserting "dummy metal" into chip designs required maintaining a large, fixed "stay-away" distance from sensitive clock signal lines ("clock nets") (Compl. ¶7). This approach was often inefficient, making it "impossible to insert enough dummy metal" to meet manufacturing density requirements in a single attempt, leading to an "involved, iterative process" that could significantly delay the design schedule (Compl. ¶26; ’259 Patent, col. 2:2-18).
- The Patented Solution: The invention claims a method that first identifies all available "free spaces" for dummy metal insertion and then prioritizes these spaces. The key step is to fill the regions adjacent to clock nets last (’259 Patent, Abstract). This approach seeks to satisfy the minimum density requirements while minimizing the adverse electrical (timing) impact on the most critical signal paths in the circuit (Compl. ¶8, ¶28; ’259 Patent, col. 2:29-38).
- Technical Importance: The method is presented as a more efficient solution that minimizes timing interference with critical clock nets while guaranteeing that the required fill density is achieved in a single pass, improving design yield and shortening production schedules (Compl. ¶9).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶28).
- The essential elements of independent claim 1 are:
- A method for inserting dummy metal into a circuit design that includes objects and clock nets.
- Identifying free spaces on a layer of the circuit design as "dummy regions."
- Prioritizing the dummy regions so that regions located adjacent to clock nets are filled with dummy metal last.
- The complaint indicates that the patent also contains independent claims directed to a computer-readable medium (Compl. ¶28) and reserves the right to assert additional claims (Compl. ¶43).
U.S. Patent No. 6,436,807 - "Method for Making an Interconnect Layer and a Semiconductor Device Including the Same"
The Invention Explained
- Problem Addressed: The patent addresses the problem that conventional methods placed dummy fill based on a "predetermined set density" without regard to the existing density of active circuit features nearby (’807 Patent, col. 2:17-21). This could result in adding unnecessary metal, which increases parasitic capacitance and degrades performance, or failing to achieve uniform density, which can cause "dishing" and "erosion" defects during polishing (Compl. ¶2-3, ¶34).
- The Patented Solution: The invention proposes a method where the density of existing active features is first determined for each layout region. Then, dummy fill is added to each specific region only as needed to achieve a "desired density" (’807 Patent, Abstract). A key aspect of the solution is defining the physical size (lateral dimension) of the dummy fill features based on a "dielectric layer deposition bias," a parameter related to the manufacturing process, to ensure proper planarization after polishing (Compl. ¶5, ¶36; ’807 Patent, col. 6:1-6).
- Technical Importance: This approach allows for more precise control over material density, which helps avoid adding unnecessary dummy fill, reduces parasitic capacitance, and facilitates uniform planarization during manufacturing (Compl. ¶37-38).
Key Claims at a Glance
- The complaint asserts independent claim 1 (Compl. ¶36).
- The essential elements of independent claim 1 are:
- A method for making a layout for an interconnect layer to facilitate uniformity of planarization.
- Determining an active interconnect feature density for each of a plurality of layout regions.
- Adding dummy fill features to each region to obtain a desired density, where the adding step comprises defining a minimum lateral dimension for the dummy fill based on a "dielectric layer deposition bias."
- The complaint reserves the right to assert additional claims (Compl. ¶56).
III. The Accused Instrumentality
Product Identification
The complaint identifies the "Accused Processes" as the circuit design methodologies used by Ampere to design semiconductor devices, with the AC7-M128-30 Altra Max device cited as a specific example (Compl. ¶1, ¶43).
Functionality and Market Context
The accused instrumentality is not a physical product but rather the design and manufacturing preparation processes for Ampere's chips (Compl. ¶44, ¶57). These processes allegedly employ electronic design automation (EDA) tools from vendors like Cadence, Synopsys, or Siemens to insert dummy metal into the chip layout. The complaint alleges these processes are used to design and manufacture products that Ampere sells in the United States and that generate substantial revenue (Compl. ¶15, ¶21).
IV. Analysis of Infringement Allegations
No probative visual evidence provided in complaint.
’259 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions | Ampere allegedly employs design tools (e.g., from Cadence, Synopsys, or Siemens) to identify free spaces on each layer of its AC7-M128-30 Altra Max's circuit designs for dummy metal insertion. | ¶45 | col. 2:30-33 |
| (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last... | The Accused Processes allegedly "assign a 'high cost' to adding metal fill near the clock nets," which results in these dummy regions being filled last, thereby minimizing timing impact on the clock nets. | ¶46 | col. 2:33-38 |
- Identified Points of Contention:
- Scope Questions: A central dispute may concern the meaning of "prioritizing... such that the... regions... are filled with dummy metal last." The court may need to determine if an alleged "cost"-based algorithm, which may de-prioritize certain areas, is equivalent to the claimed sequence where clock-net-adjacent regions are filled "last."
- Technical Questions: The complaint alleges infringement based on the general functionality of third-party EDA tools. A key question will be what evidence demonstrates that Ampere's specific implementation of these tools for the Altra Max chip performs the claimed prioritization as alleged.
’807 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) determining an active interconnect feature density for each of a plurality of layout regions of the interconnect layout | Ampere's Accused Processes allegedly employ a design tool to determine the active interconnect feature density for various layout regions of the AC7-M128-30 Altra Max's interconnect layout. | ¶58 | col. 4:24-28 |
| (b) adding dummy fill features to each layout region to obtain a desired density... the adding comprising defining a minimum dummy fill feature lateral dimension based upon a dielectric layer deposition bias... | Ampere's Accused Processes allegedly add dummy fill using design tools, and this addition comprises defining a minimum fill dimension based on a dielectric layer deposition bias. | ¶59-60 | col. 6:1-6 |
- Identified Points of Contention:
- Technical Questions: The complaint's allegation regarding the use of a "dielectric layer deposition bias" is conclusory. A critical question for the court will be whether the plaintiff can provide evidence that the accused design processes actually calculate and use this specific, technical parameter to define dummy fill dimensions, as required by the claim.
- Scope Questions: The parties may dispute what actions satisfy the step of "determining an active interconnect feature density." The question may arise whether a simple density check against a fixed threshold is sufficient, or if the claim requires a more detailed calculation as contemplated by the patent's specification.
V. Key Claim Terms for Construction
For the ’259 Patent:
- The Term: "prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last"
- Context and Importance: This phrase captures the core inventive concept. The outcome of the infringement analysis will heavily depend on whether Ampere's alleged "cost"-based system is found to meet this limitation.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The Abstract and Summary describe the concept generally: "the dummy regions are prioritized such that the dummy regions located adjacent to clock nets are filled with dummy metal last" (’259 Patent, Abstract). This language does not mandate a specific mechanism, potentially supporting an argument that any method achieving this end result qualifies.
- Evidence for a Narrower Interpretation: The detailed description discloses a specific implementation where a "Timing Factor" is calculated and the regions are sorted and filled in ascending order of this factor (’259 Patent, col. 5:35-52). This may support an argument that the claim requires a specific sorting and sequential filling process, not just a generalized de-prioritization.
For the ’807 Patent:
- The Term: "dielectric layer deposition bias"
- Context and Importance: This is a specific technical parameter that appears to be a critical limitation differentiating the invention from the prior art. Practitioners may focus on this term because infringement hinges on whether the accused processes incorporate this exact physical manufacturing characteristic into the software-based layout design.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not provide a standalone definition of the term in a glossary. A party could argue it should be given its plain and ordinary meaning to a person of ordinary skill in the art of semiconductor fabrication at the time.
- Evidence for a Narrower Interpretation: The specification describes the "bias" in the context of physical "protrusions" in a deposited dielectric layer, noting it can be "positive or negative" depending on the deposition process used (e.g., HDP-CVD) (’807 Patent, col. 2:38-48). The claims link this bias directly to "defining a minimum dummy fill feature lateral dimension" (’807 Patent, col. 6:1-6), suggesting the term is not a generic factor but is tied to specific physical phenomena of a deposition process.
VI. Other Allegations
- Indirect Infringement: The complaint alleges that Ampere infringes by "making, selling, or offering to sell in the United States, or importing into the United States products manufactured or otherwise produced using the Accused Processes" (Compl. ¶48, ¶62). These allegations appear to invoke infringement under 35 U.S.C. § 271(g) for importing products made abroad by a patented process, in addition to direct infringement under § 271(a) for using the process within the U.S.
- Willful Infringement: The complaint alleges that Ampere's infringement is "exceptional" and requests attorneys' fees pursuant to 35 U.S.C. § 285 (Compl. ¶49, ¶63). The complaint does not contain specific allegations of pre-suit knowledge of the patents. The basis for willfulness appears to rest on continued infringement after Ampere was put on notice by the filing of the lawsuit.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue for the ’259 Patent will be one of functional correspondence: does Ampere's alleged "cost"-based system for placing dummy fill, as implemented in third-party EDA tools, perform the same function in substantially the same way to achieve the same result as the claimed method of "prioritizing" regions so that those near clock nets are filled "last"?
- A key evidentiary question for the ’807 Patent will be one of technical proof: can the plaintiff produce evidence from discovery to demonstrate that Ampere's design methodology, alleged on "information and belief," actually calculates and uses a "dielectric layer deposition bias"—a specific manufacturing parameter—to define the dimensions of dummy fill features as required by the claim?
- An overarching question for the case will be one of specificity: can the plaintiff's allegations, which are broadly directed at the functionality of common EDA tools, be substantiated with specific evidence showing that Ampere's particular use and configuration of those tools for its Altra Max chip reads on the detailed, multi-step methods recited in the asserted claims?