DCT
3:22-cv-01437
Bell Semiconductor LLC v. Lattice Semiconductor Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Lattice Semiconductor Corporation (Oregon)
- Plaintiff’s Counsel: Pitzer Law; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 3:22-cv-01437, D. Or., 12/13/2022
- Venue Allegations: Plaintiff alleges venue is proper in the District of Oregon because Defendant maintains its corporate headquarters and a regular and established place of business in Hillsboro, Oregon, and commits the alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s internal semiconductor design processes infringe a patent related to a method for inserting "dummy metal" into integrated circuit layouts to improve manufacturability.
- Technical Context: The technology addresses a key challenge in semiconductor manufacturing where Chemical Mechanical Planarization (CMP) is used to flatten chip layers, a process improved by adding non-functional "dummy fill" metal, which if placed improperly can degrade circuit performance.
- Key Procedural History: The asserted patent, U.S. Patent No. 7,007,259, was the subject of an ex parte reexamination requested on December 30, 2022. On July 5, 2023, the USPTO issued a reexamination certificate confirming the patentability of all asserted independent claims, which strengthens the patent's presumption of validity.
Case Timeline
| Date | Event |
|---|---|
| 2003-07-31 | U.S. Patent No. 7,007,259 Priority Date |
| 2006-02-28 | U.S. Patent No. 7,007,259 Issue Date |
| 2022-12-13 | Complaint Filing Date (First Amended) |
| 2022-12-30 | Ex Parte Reexamination of '259 Patent Requested |
| 2023-07-05 | USPTO Issues Ex Parte Reexamination Certificate for '259 Patent |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,007,259 - Method for Providing Clock-Net Aware Dummy Metal Using Dummy Regions
- Patent Identification: U.S. Patent No. 7,007,259, Method for Providing Clock-Net Aware Dummy Metal Using Dummy Regions, issued February 28, 2006.
The Invention Explained
- Problem Addressed: The patent’s background section describes a problem in semiconductor fabrication where adding "dummy metal" is necessary for the Chemical Mechanical Polishing (CMP) process. Prior art methods used a large, fixed "stay-away" distance from critical timing circuits called "clock nets." This approach was often insufficient, making it "impossible to insert enough dummy metal into a tile to meet the required minimum density" in a single pass, forcing a costly and "involved, iterative process" that could delay production (’259 Patent, col. 2:2-18; Compl. ¶22).
- The Patented Solution: The invention is a software-based method that optimizes dummy metal insertion. It first identifies all available "dummy regions" (free spaces) in a circuit layout. Crucially, it then prioritizes these regions so that those "located adjacent to clock nets are filled with dummy metal last" (’259 Patent, Abstract). By deferring the fill of these sensitive areas, the method aims to meet the required metal density for CMP while minimizing negative impacts on circuit timing, all within a single automated run (’259 Patent, col. 2:19-23). The process flow is illustrated in Figure 5, which shows sorting dummy regions based on a "timing factor" before insertion begins (’259 Patent, Fig. 5).
- Technical Importance: This "clock-net aware" approach provided a more efficient solution that could accommodate the increasingly high-density requirements of modern chip designs without the manual, multi-run process required by prior art tools (Compl. ¶23).
Key Claims at a Glance
- The complaint focuses on independent Claim 1, though it references three independent claims in total (’259 Patent, claims 1, 18, 35; Compl. ¶24).
- The essential elements of independent Claim 1 are:
- A method for inserting dummy metal into a circuit design that includes objects and clock nets.
- (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions, and
- (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets.
- The complaint alleges infringement of "one or more claims" of the patent, suggesting that dependent claims may also be asserted (Compl. ¶31).
III. The Accused Instrumentality
Product Identification
- The primary accused instrumentality is not a commercial product but rather the internal design methodologies ("Accused Processes") that Lattice Semiconductor allegedly uses to design its chips (Compl. ¶32). The complaint identifies the Lattice LCMX02-7000HC semiconductor device as one example product created using these allegedly infringing processes (Compl. ¶31).
Functionality and Market Context
- The complaint alleges that Lattice employs industry-standard design tools from vendors such as Cadence, Synopsys, or Siemens to implement its Accused Processes (Compl. ¶32). The specific functionality at issue is the method used to insert dummy metal into its circuit designs. It is alleged that these processes operate by assigning a "high cost" to adding metal fill near clock nets and a "lower cost" to filling areas near other nets (Compl. ¶34). This cost-based differentiation allegedly results in the regions near clock nets being filled last, mirroring the patented method (Compl. ¶34). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
- ’259 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| A method for inserting dummy metal into a circuit design, the circuit design including a plurality of objects and clock nets... | Lattice uses design tools to perform a method of inserting dummy metal into the design for its LCMX02-7000HC device, which contains objects and clock nets. | ¶32 | col. 2:26-30 |
| (a) identifying free spaces on each layer of the circuit design suitable for dummy metal insertion as dummy regions, | Lattice's Accused Processes, using design tools, identify free spaces on each layer of its device's circuit designs suitable for dummy metal insertion. | ¶33 | col. 3:36-40 |
| (b) prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last, thereby minimizing any timing impact on the clock nets. | The Accused Processes allegedly assign a "high cost" to filling regions near clock nets and a "lower cost" elsewhere, which prioritizes these regions to be filled last. | ¶34 | col. 2:32-35 |
- Identified Points of Contention:
- Scope Questions: A central dispute may arise over the meaning of "filled with dummy metal last." The defense could argue this requires an absolute finality—that no metal is placed in clock-net-adjacent regions until all other regions are completely filled. The complaint’s allegation of a "high cost" function raises the question of whether a cost-based preference system, which may not guarantee absolute finality, meets this limitation literally.
- Technical Questions: The complaint's infringement theory rests on the factual assertion that Lattice's design tools use a "cost" function that directly corresponds to the claimed "prioritizing" step (Compl. ¶34). The case will likely require evidence from discovery concerning the specific algorithms and parameters used within Lattice's design automation software to determine if they in fact perform this function as alleged.
V. Key Claim Terms for Construction
The Term: "prioritizing the dummy regions such that the dummy regions located adjacent to clock nets are filled with dummy metal last"
Context and Importance: This phrase contains the core inventive concept and is central to the infringement analysis. The outcome of the case may depend on whether Lattice's alleged "high cost" system is construed to fall within the scope of this limitation. Practitioners may focus on this term because the difference between a hard-coded "last" step and a probabilistic "lowest priority" step is a critical technical distinction.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent describes sorting a "dummy region list... in ascending order of the timing factor" and then inserting metal sequentially (’259 Patent, col. 5:35-51). This could support a construction where "last" means having the lowest priority in a sorted sequence, which a "high cost" could achieve.
- Evidence for a Narrower Interpretation: The patent states that by using this method, "in many cases, no dummy metal... is inserted in the clock-net adjacent dummy regions" (’259 Patent, col. 6:60-64). This could support a narrower construction where "last" implies that these regions are only filled as a final resort after all other non-adjacent areas are exhausted.
The Term: "adjacent to clock nets"
Context and Importance: This term defines the physical scope of the regions subject to the "fill last" rule. Its construction will determine which areas within the accused design process must follow the prioritization logic.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent does not provide an explicit definition for "adjacent," which may lead parties to argue for its plain and ordinary meaning of "close to or near."
- Evidence for a Narrower Interpretation: The specification describes a step of tagging dummy regions "located immediately adjacent to the clock net wire" (’259 Patent, col. 4:30-32, emphasis added). The use of "immediately" could be cited to argue for a more restrictive definition requiring direct physical contact.
VI. Other Allegations
- Indirect Infringement: The complaint does not plead specific facts to support claims of induced or contributory infringement. The allegations focus on direct infringement by Lattice through its use of the Accused Processes in the United States (Compl. ¶31, 36).
- Willful Infringement: The complaint makes a conclusory allegation that infringement is "exceptional" under 35 U.S.C. § 285 but does not plead specific facts to support a claim of willfulness, such as alleging that Lattice had pre-suit knowledge of the ’259 patent (Compl. ¶37).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of claim construction: Can the limitation "filled with dummy metal last" be satisfied by a "cost-based" software function that assigns the lowest priority to certain regions, or does it require a more rigid, absolute final step in the fill sequence?
- A key evidentiary question will be one of technical proof: What evidence will emerge from discovery to show how Lattice's design automation tools actually work, and will that evidence demonstrate that they perform the specific prioritization function required by Claim 1 as construed by the court?
- A central strategic question will be the impact of the reexamination: Given that the asserted independent claims have survived a reexamination, the case may focus more intensely on infringement and damages, as the patent's validity is now reinforced against challenges based on prior art.