DCT
3:22-cv-01542
Bell Semiconductor LLC v. Lattice Semiconductor Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Bell Semiconductor, LLC (Delaware)
- Defendant: Lattice Semiconductor Corporation (Oregon)
- Plaintiff’s Counsel: Pitzer Law; Devlin Law Firm LLC; McKool Smith, P.C.
- Case Identification: 3:22-cv-01542, D. Or., 12/07/2022
- Venue Allegations: Venue is asserted based on Defendant's corporate headquarters and principal place of business being located in the District of Oregon, constituting a regular and established place of business where alleged acts of infringement occur.
- Core Dispute: Plaintiff alleges that Defendant’s internal processes for designing semiconductor chips infringe a patent related to efficiently implementing engineering change orders in an integrated circuit design.
- Technical Context: The technology lies in the field of electronic design automation (EDA), addressing the challenge of modifying complex semiconductor layouts without requiring a full, time-consuming redesign for minor changes.
- Key Procedural History: The operative pleading is a First Amended Complaint. The complaint does not mention any prior litigation, inter partes review (IPR) proceedings, or licensing history related to the patent-in-suit.
Case Timeline
| Date | Event |
|---|---|
| 2004-12-17 | ’626 Patent Priority Date |
| 2007-06-12 | ’626 Patent Issue Date |
| 2022-12-07 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,231,626 - "Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows," issued June 12, 2007
The Invention Explained
- Problem Addressed: The patent's background section describes prior art methods for making a small engineering change order (ECO) to a large, complex integrated circuit (IC) design as highly inefficient (’626 Patent, col. 2:15-22). In these prior methods, design tools such as routers and validators had to be run on the entire IC design, even if the change affected only a few cells, leading to long turnaround times (e.g., one week) and significant computational expense (Compl. ¶¶24-25; ’626 Patent, col. 2:36-44).
- The Patented Solution: The invention proposes a method to localize the impact of an ECO. It involves creating a "window"—a defined sub-region of the IC design that encloses the change—and performing computationally intensive steps like routing and verification only on the data within that window (’626 Patent, Abstract). The results from this localized process are then merged into a copy of the overall design to create a revised version, thereby isolating the required computation to the area of the change (Compl. ¶4; ’626 Patent, col. 4:1-24).
- Technical Importance: This method aims to make the time required to implement an ECO dependent on the size of the change itself, rather than the size of the entire IC, offering significant savings in time and resources in the semiconductor design cycle (Compl. ¶29; ’626 Patent, col. 2:48-53).
Key Claims at a Glance
- The complaint asserts infringement of one or more claims, with a focus on independent method claim 1 (Compl. ¶¶30, 37).
- The essential elements of independent claim 1 include:
- Receiving as input an integrated circuit design and an engineering change order;
- Creating at least one "window" in the design that encloses the change, where the window is smaller than the entire design area;
- Performing "incremental routing" only for nets enclosed by the window;
- "Replacing an area in a copy" of the original design with the results of the incremental routing to generate a revised design; and
- Generating the revised integrated circuit design as output.
- The complaint alleges infringement of "one or more claims," which suggests the right to assert dependent claims may be preserved (Compl. ¶37).
III. The Accused Instrumentality
Product Identification
- The complaint identifies the "Accused Processes" as the methodologies used by Lattice to design its semiconductor devices, with the "Lattice PS2251-17-43" chip cited as at least one specific product made using these processes (Compl. ¶¶1, 37-38).
Functionality and Market Context
- The complaint alleges that Lattice's design workflow constitutes the infringing method. Specifically, it alleges that when implementing an ECO, Lattice uses EDA tools (from providers such as Cadence, Synopsys, and/or Siemens) to perform "incremental routing" (Compl. ¶38). This allegedly involves routing only the nets affected by the ECO and then "merging that changed area into the overall circuit layout" to create a revised design (Compl. ¶38). The complaint further alleges that related steps, such as parasitic extraction and design rule checks, are also performed only on the nets within the defined ECO window (Compl. ¶¶39-40). The complaint asserts these patented processes provide significant commercial value for chip designers but provides no specific market context for the accused PS2251-17-43 chip (Compl. ¶28).
IV. Analysis of Infringement Allegations
The complaint does not include a claim chart but describes the alleged infringement in narrative form and references an expert declaration in an unattached exhibit (Compl. ¶¶37-41). The allegations for the lead asserted claim are summarized below.
No probative visual evidence provided in complaint.
’626 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) receiving as input an integrated circuit design; | Lattice receives or inputs an IC design at the start of its design process. | ¶37 | col. 6:52-53 |
| (b) receiving as input an engineering change order to the integrated circuit design; | Lattice implements ECOs as part of its design methodology for its semiconductor devices. | ¶38 | col. 6:54-55 |
| (c) creating at least one window in the integrated circuit design that encloses a change to the integrated circuit design... wherein the window... is less than an entire area of the integrated circuit design; | The Accused Processes allegedly define a "window" for the ECO that is smaller than the full design, inside which subsequent steps are performed. | ¶¶39, 40 | col. 6:56-62 |
| (d) performing an incremental routing of the integrated circuit design only for each net in the integrated circuit design that is enclosed by the window; | Lattice allegedly "perform[s] a method for only routing the nets affected by the ECO" using third-party EDA tools. | ¶38 | col. 6:63-65 |
| (e) replacing an area in a copy of the integrated circuit design... with results of the incremental routing to generate a revised integrated circuit design; | Lattice's process is alleged to merge the "changed area into the overall circuit layout... to generate a revised integrated circuit design." | ¶38 | col. 7:1-5 |
| (f) generating as output the revised integrated circuit design. | Lattice's process ultimately generates a revised IC design as the output of implementing the ECO. | ¶38 | col. 7:6-7 |
- Identified Points of Contention:
- Scope Questions: The complaint alleges that Lattice's use of general-purpose, third-party EDA tools constitutes infringement (Compl. ¶38). A central dispute may be whether Lattice's specific configuration and use of these tools meets every limitation of the asserted claims. The functionality of the EDA tools themselves versus how Lattice specifically employs them will be a critical distinction.
- Technical Questions: The complaint's allegations are made on "information and belief" (Compl. ¶37). A key evidentiary question will be whether discovery reveals that Lattice's actual, internal design flow for the accused products maps onto the specific steps of the claims. For example, what evidence demonstrates that Lattice's process performs routing only for nets enclosed by a defined window and then "replaces" that area in a "copy" of the design, as opposed to modifying the original design data in-place?
V. Key Claim Terms for Construction
The Term: "window"
- Context and Importance: This term is the core of the invention, defining the localized area where operations are performed. Its construction will determine the scope of the claims and what level of spatial and logical segmentation is required to infringe.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification provides a high-level definition: "The term 'window' as used herein is defined as a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 4:59-62). This could support an argument that any defined sub-region within an EDA tool meets the limitation.
- Evidence for a Narrower Interpretation: The patent also describes a specific algorithm for creating the window, which involves calculating bounding boxes around changed port instances and merging them (’626 Patent, Fig. 3; col. 5:1-11). A party could argue that a "window" is not just any sub-region but must be one created by a process analogous to the one disclosed.
The Term: "replacing an area in a copy of the integrated circuit design"
- Context and Importance: This limitation describes how the localized changes are integrated into the full design. Whether the accused process operates on a "copy" or modifies the original data could be a dispositive issue for infringement.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A plaintiff might argue that loading a design file into a computer's memory for processing inherently creates a "copy" and that subsequent modifications to that in-memory data satisfy the claim element.
- Evidence for a Narrower Interpretation: The language specifies replacing contents "in a copy of the original integrated circuit design" (’626 Patent, col. 4:20-22). A defendant might argue this requires the creation of a distinct, duplicate design file, and that an in-place modification of the original data file does not meet this limitation.
VI. Other Allegations
- Indirect Infringement: The complaint's primary focus is on direct infringement by Lattice's use of the patented method under 35 U.S.C. § 271(a) (Compl. ¶37). While it includes boilerplate language referring to § 271 et. seq., it does not plead specific facts to support claims of induced or contributory infringement (Compl. ¶43).
- Willful Infringement: The complaint does not use the word "willful." However, it alleges that Lattice's infringement is "exceptional and entitles Bell Semic to attorneys' fees" under 35 U.S.C. § 285 (Compl. ¶44). This allegation, combined with the assertion that Lattice "continues to infringe" (Compl. ¶42), lays the groundwork for a potential finding of willful or egregious conduct, particularly for any infringement occurring after the complaint was filed.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of evidentiary proof: Can the Plaintiff, through discovery, produce specific evidence that Defendant's confidential, internal design methodology for the accused chips practices each step of the asserted method claim? The case may turn on moving from general allegations about the capabilities of EDA tools to concrete proof of the Defendant's actual workflow.
- The case will also involve a key question of claim scope: Can the term "window," as used in the patent, be construed to cover any user-defined sub-region in a standard EDA tool, or is it limited to a more specific, algorithmically-generated boundary as described in the patent's preferred embodiments? The answer will likely determine whether the use of common, off-the-shelf design software can constitute infringement.