Bell Semiconductor LLC v. Ampere Computing LLC

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Bell Semiconductor, LLC (Delaware)
  • Defendant: Ampere Computing, LLC (Delaware, with principal place of business in California)
  • Plaintiff’s Counsel: Pitzer Law; Devlin Law Firm LLC; McKool Smith, P.C.
• Case Identification: 3:22-cv-01903, D. Or., 12/08/2022
• Venue Allegations: Plaintiff alleges venue is proper in the District of Oregon because Defendant maintains a regular and established place of business in Portland, Oregon.
• Core Dispute: Plaintiff alleges that Defendant’s processes for designing semiconductor chips, such as the AC7-M128-30 Altra Max, infringe patents related to efficient implementation of engineering changes and reduction of interlayer capacitance.
• Technical Context: The technologies at issue address key challenges in modern integrated circuit (IC) design: efficiently modifying complex circuit layouts and mitigating performance degradation caused by parasitic electronic effects during fabrication.
• Key Procedural History: The complaint does not mention any prior litigation, Inter Partes Review (IPR) proceedings, or licensing history related to the patents-in-suit.

Case Timeline

Date	Event
2004-11-17	’760 Patent Priority Date
2004-12-17	’626 Patent Priority Date
2007-06-12	’626 Patent Issue Date
2008-07-08	’760 Patent Issue Date
2022-12-08	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,231,626, “Method Of Implementing An Engineering Change Order In An Integrated Circuit Design By Windows,” issued June 12, 2007

The Invention Explained

• Problem Addressed: The patent’s background section describes that prior methods for implementing an engineering change order (ECO) in an IC design were highly inefficient. Design tools had to be run for the entire circuit design, even for a minor change, resulting in a typical turnaround time of about one week regardless of the ECO’s size (Compl. ¶¶29-30; ’626 Patent, col. 2:15-22, 2:37-44).
• The Patented Solution: The invention proposes a method to localize the impact of an ECO. It involves creating a "window" that encloses only the area of the circuit affected by the change. Computationally intensive processes, like routing, are then performed only for the circuit nets within this window. The updated window is then merged back into a copy of the overall design, creating a revised circuit without processing the entire layout (Compl. ¶4; ’626 Patent, col. 3:19-23).
• Technical Importance: This approach makes the time required to implement a design change dependent on the size of the change itself, rather than the size of the entire IC, substantially reducing design cycle time and costs (Compl. ¶¶32, 34; ’626 Patent, col. 2:50-53).

Key Claims at a Glance

• The complaint asserts claims including independent claim 1 (Compl. ¶35; Compl. Ex. B).
• Independent Claim 1 elements include:
  • receiving as input an integrated circuit design;
  • receiving as input an engineering change order;
  • creating at least one window in the design that encloses the change, where the window is smaller than the entire design area;
  • performing an incremental routing of the design only for each net enclosed by the window;
  • replacing an area in a copy of the design with the results of the incremental routing; and
  • generating the revised integrated circuit design as output.
• The complaint’s infringement analysis addresses dependent claims 2-4 as well (Compl. Ex. B).

U.S. Patent No. 7,396,760, “Method and System for Reducing Inter-Layer Capacitance in Integrated Circuits,” issued July 8, 2008

The Invention Explained

• Problem Addressed: The patent addresses a problem arising from the use of "dummy fill"—non-functional material added to IC layers to ensure surface uniformity for manufacturing processes like Chemical Mechanical Planarization (CMP). Prior art methods focused on fill density within a single layer (intralayer) but ignored the negative impact of dummy fill features overlapping on successive layers. This overlap creates unwanted "interlayer bulk capacitance," which slows down signals and degrades circuit performance (Compl. ¶¶6-8, 43; ’760 Patent, col. 1:62-2:6).
• The Patented Solution: The invention provides a method that considers pairs of consecutive layers together. It identifies potential overlaps between dummy fill spaces on adjacent layers and re-arranges the fill features to minimize this overlap. One described embodiment is arranging the fill features in a checkerboard pattern, such that a feature on one layer is offset from features on the layer below it, thereby reducing the area of overlap and the resulting capacitance (Compl. ¶¶9-10; ’760 Patent, col. 2:7-13, Abstract).
• Technical Importance: By actively managing interlayer capacitance from dummy fill, a factor previously unaddressed, the invention improves the speed and performance of the final integrated circuit (Compl. ¶11; ’760 Patent, col. 2:3-6).

Key Claims at a Glance

• The complaint asserts claims including independent claim 1 (Compl. ¶45; Compl. Ex. E).
• Independent Claim 1 elements include:
  • obtaining layout information of an IC with a plurality of layers;
  • obtaining a first dummy fill space for a first layer;
  • obtaining a second dummy fill space for a successive second layer;
  • determining an overlap between the first and second dummy fill spaces; and
  • minimizing the overlap by re-arranging a plurality of first and second dummy fill features.
  • The claim further specifies that the dummy fill spaces include non-signal carrying lines.
• The complaint’s infringement analysis also addresses dependent claims 2-6 and 11-13 (Compl. Ex. E).

III. The Accused Instrumentality

Product Identification

• The accused instrumentalities are the processes ("Accused Processes") used by Ampere to design its semiconductor devices, including its AC7-M128-30 Altra Max chip (Compl. ¶¶1, 53, 67). These processes allegedly employ electronic design automation (EDA) tools from vendors such as Cadence, Synopsys, and/or Siemens (Compl. ¶¶53, 67).

Functionality and Market Context

• The complaint alleges that Ampere uses these EDA tools to perform the patented methods. For the ’626 Patent, this involves using the tools to perform incremental routing within a defined window to implement an ECO (Compl. ¶53). For the ’760 Patent, this involves using the tools to rearrange dummy fill material between successive layers to minimize overlap and reduce interlayer capacitance in a timing-aware manner (Compl. ¶67). An image provided in the complaint shows the Ampere Computing Altra Max server product which incorporates the accused chips (Compl. Ex. E, p. 106). The Altra Max processor is a high-performance ARM-based CPU targeted at cloud and data center markets (Compl. ¶1).

IV. Analysis of Infringement Allegations

’626 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
(a) receiving as input an integrated circuit design;	The Accused Processes receive an IC design as input, for example, by importing a design into a Cadence tool.	¶53; Ex. B, p. 38	col. 6:49-50
(b) receiving as input an engineering change order to the integrated circuit design;	The Accused Processes receive an ECO as input, which specifies changes to the IC design.	¶53; Ex. B, p. 39	col. 6:51-52
(c) creating at least one window...that encloses a change...wherein the window...is less than an entire area of the integrated circuit design;	The Accused Processes allegedly use commands to define a bounded edit area (a "window") that is smaller than the full chip layout to implement the ECO. A figure in the complaint depicts multiple such edit areas on a chip layout.	¶53; Ex. B, p. 41	col. 6:53-59
(d) performing an incremental routing of the integrated circuit design only for each net...that is enclosed by the window;	The Accused Processes allegedly perform routing and design rule checks only for the nets contained within the defined edit area.	¶53, 55; Ex. B, p. 42	col. 6:60-63
(e) replacing an area in a copy of the integrated circuit design...with results of the incremental routing to generate a revised integrated circuit design; and	The Accused Processes allegedly merge the results from the incremental routing within the edit area back into a copy of the main design database.	¶53; Ex. B, p. 44	col. 6:64-67
(f) generating as output the revised integrated circuit design.	The Accused Processes generate the final, revised IC design as an output file.	¶53; Ex. B, p. 44	col. 7:4-5

Identified Points of Contention

• Scope Questions: A potential issue may be whether the "parallel edit" functionality of modern EDA tools, which allows multiple designers to work on different "areas" of a chip simultaneously, constitutes "creating at least one window... that encloses a change" for an ECO as contemplated by the patent. The defense may argue these are distinct concepts for workflow management versus specific ECO implementation.
• Technical Questions: The complaint alleges on "information and belief" that routing and other checks are performed only for nets within the window. A factual question will be what evidence demonstrates this limitation, as opposed to the tool analyzing a broader set of nets that might be electrically affected by the change but extend beyond the window's physical boundaries.

’760 Patent Infringement Allegations

Claim Element (from Independent Claim 1)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
(a) obtaining layout information of the integrated circuit...including a plurality of layers;	The Accused Processes obtain the IC layout information, which includes multiple layers, by loading the design into an EDA tool.	¶67; Ex. E, p. 108	col. 6:9-11
(b) obtaining a first dummy fill space for a first layer...; (c) obtaining a second dummy fill space for a second layer...;	The Accused Processes allegedly identify available spaces for inserting dummy fill on a first layer and a successive second layer based on the layout information and density requirements.	¶67; Ex. E, p. 109	col. 6:12-17
(d) determining an overlap between the first dummy fill space and the second dummy fill space; and	The Accused Processes allegedly determine where dummy fill on the first and second layers would overlap. The complaint asserts this step is a prerequisite for staggering the fill.	¶67; Ex. E, p. 110	col. 6:18-20
(e) minimizing the overlap by re-arranging a plurality of first dummy fill features and a plurality of second dummy fill features;	The Accused Processes allegedly rearrange or "stagger" dummy fill features in successive layers to minimize their vertical overlap and the resulting interlayer capacitance.	¶67; Ex. E, p. 111	col. 6:21-24
(f) wherein the first dummy fill space includes non-signal carrying lines...and the second dummy fill space includes non-signal carrying lines...	This is met by the inherent definition of dummy fill, which consists of non-signal carrying features.	¶67; Ex. E, p. 113	col. 6:25-29

Identified Points of Contention

• Scope Questions: The case may turn on whether the accused tools' automated "staggered fill" function meets the claim limitation of "minimizing the overlap by re-arranging." The defense could argue that applying a default staggered pattern is not the same as the patent's more deliberative process of determining an overlap and then actively re-arranging features to minimize it.
• Technical Questions: What evidence does the complaint provide that the Accused Processes perform a discrete step of "determining an overlap" before applying a staggered fill? A central question is whether the EDA tool's algorithm explicitly identifies and minimizes overlaps, or if it simply applies a geometric pattern (e.g., an offset grid) that has the effect of reducing overlap without performing the claimed "determining" step.

V. Key Claim Terms for Construction

Term from the ’626 Patent: "window"

• Context and Importance: This term is the central pillar of the '626 patent's claims. Its construction will determine whether the functionality of modern EDA tools, such as defining "edit areas," falls within the scope of the invention. Practitioners may focus on this term because the defense could argue that their tool's "areas" are for user management in a parallel design environment, not the specific, ECO-driven "window" creation process described in the patent.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification provides a broad structural definition: "a rectilinear boundary that encloses an area of the integrated circuit design that is less than the entire area of the integrated circuit design" (’626 Patent, col. 3:58-62). This language could support reading the term on any bounded sub-region of the design.
  • Evidence for a Narrower Interpretation: The detailed description of an embodiment specifies a more functional creation process, where the window is formed by calculating a "bounding box that includes the port instances for each net changed by the engineering change order" (’626 Patent, col. 4:58-62). This could support a narrower construction tied to the specific nets affected by the ECO.

Term from the ’760 Patent: "minimizing the overlap by re-arranging"

• Context and Importance: This active step is the core of the ’760 patent's method. The infringement dispute will likely hinge on whether the accused EDA tool's function of applying a "staggered" fill pattern is equivalent to this claimed step.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The specification describes the outcome as ensuring dummy fill features "are not placed directly above the ones on the second layer but offset from each other" (’760 Patent, col. 4:39-42). This focus on the result (an offset) could support a broader interpretation where any process that achieves this offset is "minimizing by re-arranging."
  • Evidence for a Narrower Interpretation: The patent’s flow chart (FIG. 3) depicts a sequence of discrete logical steps: determining if there is an overlap, determining if it is avoidable, and then performing the "Re-arrange dummy fill features" step (’760 Patent, FIG. 3). This suggests a more complex process of analysis followed by a responsive rearrangement, rather than the simple application of a default geometric pattern.

VI. Other Allegations

• Indirect Infringement: The complaint alleges infringement pursuant to 35 U.S.C. § 271, et. seq., which encompasses indirect infringement (Compl. ¶¶58, 71). However, the factual allegations focus exclusively on Defendant's alleged direct infringement by its own use of the Accused Processes to design chips. The complaint does not plead specific facts to support claims of induced or contributory infringement, such as allegations that Ampere instructed others to perform the patented methods.
• Willful Infringement: The complaint does not explicitly allege "willful infringement" or plead facts regarding pre-suit knowledge of the patents-in-suit. It does, however, allege that Ampere's infringement is "exceptional" and seeks attorneys' fees under 35 U.S.C. § 285 (Compl. ¶¶59, 72).

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of definitional scope: can the term "window," described in the '626 patent as a construct for implementing a specific engineering change order, be construed to cover the "parallel edit areas" of modern EDA software, which are also used for broader, collaborative design workflow management?
• A central question will be one of functional equivalence: does an EDA tool’s automated function for applying a "staggered" dummy fill pattern perform the specific, multi-part logical method of "determining an overlap" and then "minimizing the overlap by re-arranging" as required by claim 1 of the '760 patent, or is there a fundamental mismatch in the technical operation?
• The case will also present an evidentiary challenge: given that the allegations are based on "information and belief" from public-facing documents, the outcome may depend heavily on whether discovery reveals that Ampere's internal design methodologies and actual use of its EDA tools map directly onto the specific, ordered steps recited in the asserted claims.