DCT
2:04-cv-00377
Opti Inc v. NVIDIA Corpation
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: OPTi Inc. (California)
- Defendant: nVidia Corporation (Delaware)
- Plaintiff’s Counsel: McKool Smith, PC; Winston & Strawn, LLP; Proskauer Rose LLP
- Case Identification: 2:04-cv-00377, E.D. Tex., 10/19/2004
- Venue Allegations: The complaint alleges that venue is proper under 28 U.S.C. §§ 1391(b) and 1400(b) without providing a detailed factual basis.
- Core Dispute: Plaintiff alleges that Defendant’s nForce series of media and communications processors infringes five patents related to predictive cache memory snooping and compact bus interfaces.
- Technical Context: The patents address methods for improving data transfer efficiency in personal computers, a critical area for performance enhancement during the widespread adoption of the PCI bus architecture.
- Key Procedural History: The complaint does not specify any prior litigation or licensing history. U.S. Patent No. 5,813,036 is a divisional of the application that led to U.S. Patent No. 5,710,906, and U.S. Patent No. 6,405,291 is a continuation in the same patent family. U.S. Patent No. 6,098,141 is a continuation of the application that led to U.S. Patent No. 5,944,807.
Case Timeline
| Date | Event |
|---|---|
| 1995-07-07 | Priority Date for ’906, ’036, and ’291 Patents |
| 1996-02-06 | Priority Date for ’807 and ’141 Patents |
| 1998-01-20 | U.S. Patent No. 5,710,906 Issued |
| 1998-09-22 | U.S. Patent No. 5,813,036 Issued |
| 1999-08-31 | U.S. Patent No. 5,944,807 Issued |
| 2000-08-01 | U.S. Patent No. 6,098,141 Issued |
| 2002-06-11 | U.S. Patent No. 6,405,291 Issued |
| 2004-10-19 | Complaint Filed |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 5,710,906 - "Predictive Snooping of Cache Memory for Master-Initiated Accesses"
The Invention Explained
- Problem Addressed: In computer systems using a PCI bus, a "bus master" device can transfer large blocks of data in a "burst." A technical problem arises when this burst transfer crosses a cache line boundary in the system's memory. Conventional systems must pause the transfer to perform an "inquire cycle" (or "snoop") to ensure data coherency with the CPU's cache, which hampers performance and can violate PCI bus timing specifications (Compl., Ex. 1, ’906 Patent, col. 5:40-64).
- The Patented Solution: The invention proposes a "predictive" snooping mechanism. Instead of waiting for the burst to cross the boundary, the system controller "simultaneously and predictively, performs an inquire cycle of the L1 cache for the next cache line" while the data transfer for the current line is still in progress. This anticipatory action ensures that the snoop cycle is already complete or underway when the boundary is crossed, allowing the burst transfer to proceed with minimal or no delay (Compl., Ex. 1, ’906 Patent, col. 6:8-23).
- Technical Importance: This approach aimed to allow PCI bus masters to achieve the full high-speed data transfer rates promised by the PCI protocol without being bottlenecked by cache coherency checks (Compl., Ex. 1, ’906 Patent, col. 6:1-4).
Key Claims at a Glance
The complaint does not identify specific asserted claims. The following analysis is based on Claim 1 as a representative independent claim.
- Independent Claim 1 is a method claim for transferring data between a bus master and secondary memory, which includes the following essential elements:
- Sequentially transferring data units beginning at a starting memory location and continuing beyond a cache line boundary.
- Initiating a "next-line inquiry" to check the cache for the subsequent memory line.
- Crucially, this next-line inquiry is initiated prior to completion of the transfer of the last data unit before the cache line boundary is crossed.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 5,813,036 - "Predictive Snooping of Cache Memory for Master-Initiated Accesses"
The Invention Explained
- Problem Addressed: The ’036 Patent, a divisional of the application that led to the ’906 Patent, addresses the same technical problem of performance degradation when a PCI-bus master's burst access crosses a cache line boundary (Compl., Ex. 2, ’036 Patent, col. 5:40-64).
- The Patented Solution: The solution is the same predictive snooping method described in the ’906 Patent, where the system controller initiates a snoop of the next cache line before the ongoing burst transfer has reached the boundary (Compl., Ex. 2, ’036 Patent, col. 6:8-23).
- Technical Importance: This patent protects the apparatus/controller that implements the predictive snooping method, complementing the method claims of the parent ’906 Patent (Compl., Ex. 2, ’036 Patent, col. 6:1-4).
Key Claims at a Glance
The complaint does not identify specific asserted claims. The following analysis is based on Claim 1 as a representative independent claim.
- Independent Claim 1 is an apparatus claim for a controller, comprising:
- Means for sequentially transferring data units between a bus master and secondary memory, continuing beyond a cache line boundary.
- Means for initiating a "next-line inquiry" to determine if the next cache line is in a modified state in the first cache memory.
- This initiation occurs prior to completion of the transfer of the last data unit before the boundary.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 6,405,291 - "Predictive Snooping of Cache Memory for Master-Initiated Accesses"
- Technology Synopsis: As a continuation in the same family as the ’906 and ’036 patents, this patent also relates to predictive snooping of cache memory during burst accesses initiated by a bus master to avoid performance degradation at cache line boundaries (Compl., Ex. 5, ’291 Patent, Abstract).
- Asserted Claims: The complaint does not specify which claims are asserted (Compl. ¶12).
- Accused Features: The complaint accuses the memory and cache control functionalities of nVidia's nForce chipsets (Compl. ¶12).
U.S. Patent No. 5,944,807 - "Compact ISA-bus Interface"
- Technology Synopsis: This patent addresses the problem of the large number of pins required for a standard ISA bus interface. It proposes a "compact" interface that multiplexes address, data, command, and other information onto a single, smaller bus to reduce pin count while maintaining ISA-compatible operation (Compl., Ex. 3, ’807 Patent, Abstract).
- Asserted Claims: The complaint does not specify which claims are asserted (Compl. ¶17).
- Accused Features: The complaint accuses the bus interface functionalities of nVidia's nForce chipsets (Compl. ¶17).
U.S. Patent No. 6,098,141 - "Compact ISA-bus Interface"
- Technology Synopsis: A continuation of the application for the ’807 Patent, this patent also describes a reduced pin-count I/O interface that uses a single, multiplexed bus for address, data, and command signals to achieve ISA-compatible operation (Compl., Ex. 4, ’141 Patent, Abstract).
- Asserted Claims: The complaint does not specify which claims are asserted (Compl. ¶17).
- Accused Features: The complaint accuses the bus interface functionalities of nVidia's nForce chipsets (Compl. ¶17).
III. The Accused Instrumentality
Product Identification
- The complaint accuses "chipsets, including without limitation one or more of its series of nForce media and communications processors" (Compl. ¶12, ¶17).
Functionality and Market Context
- The complaint broadly identifies the accused products as "chipsets" and "media and communications processors" but does not provide specific technical details about their architecture or operation (Compl. ¶12, ¶17). The allegations suggest these chipsets are components used in computer systems made by third parties (Compl. ¶13, ¶18). No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint does not contain a claim chart or provide specific factual allegations mapping the features of the accused products to the elements of the asserted claims. The following illustrative charts are based on the representative independent claims identified in Section II and the general allegation that the nVidia nForce chipsets infringe.
’906 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| sequentially transferring data units between said bus master and said secondary memory...and continuing beyond an l-byte boundary of said secondary memory address space | The functionality of the nForce chipsets that manages burst data transfers from system memory to a bus master across cache line boundaries. | ¶12 | col. 30:8-14 |
| initiating a next-line inquiry, prior to completion of the transfer of the last data unit before said l-byte boundary, to determine whether an N+1'th l-byte line...is cached in a modified state | The alleged predictive snooping function within the nForce chipsets that checks the CPU cache for the next memory line ahead of time. | ¶12 | col. 30:15-24 |
’036 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| means for sequentially transferring a plurality of data units between a bus master and a memory...said sequentially transferred data units continuing sequentially beyond an l-byte boundary of said first cache memory | The hardware components within the nForce chipsets responsible for executing burst data transfers that cross cache line boundaries. | ¶12 | col. 29:50-57 |
| means for, after completing the snoop of said first level cache for said starting line, automatically snooping said first level cache for a next sequential line after said starting line without waiting for said transfer to reach the end of said starting line | The hardware logic within the nForce chipsets allegedly configured to automatically and predictively initiate a snoop of the subsequent cache line. | ¶12 | col. 29:58-64 |
Identified Points of Contention
- Technical Questions: A primary evidentiary question will concern the actual operation of the accused nForce chipsets. What proof does the Plaintiff have that the chipsets' memory controllers initiate a snoop for a subsequent cache line before the transfer of the last data unit of the current cache line is complete? The specific timing and internal logic of the accused hardware will be central.
- Scope Questions: The patents-in-suit are heavily grounded in the context of Pentium-era processors and the PCI bus specification (Compl., Ex. 1, ’906 Patent, col. 5:1-7). A potential point of contention may be whether the term "sequentially transferring data units" is limited to the specific PCI "linear burst mode" described in the patent, or if it can be construed more broadly to cover different bus protocols or transfer modes used by the accused nForce products.
V. Key Claim Terms for Construction
The complaint does not provide sufficient detail for analysis of specific claim construction disputes. However, based on the technology, certain terms may become focal points.
- The Term: "initiating a next-line inquiry, prior to completion of the transfer of the last data unit before said l-byte boundary" ('906 Patent, Claim 1)
- Context and Importance: This temporal limitation appears to be the core of the claimed invention. The entire dispute may hinge on whether the accused devices meet this precise timing requirement. Practitioners may focus on this term because it defines the "predictive" nature of the invention, distinguishing it from prior art that might have snooped only after a boundary was crossed.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification's stated goal is to allow "the burst to proceed with, at most, a short delay," which may support a construction that encompasses any anticipatory snoop that achieves this functional outcome, regardless of the precise clock-cycle implementation (Compl., Ex. 1, ’906 Patent, col. 6:21-23).
- Evidence for a Narrower Interpretation: The detailed description and timing diagrams (e.g., FIG. 4) illustrate a very specific implementation, showing the EADS# signal being asserted at a particular clock cycle relative to ongoing data transfers (Compl., Ex. 1, ’906 Patent, col. 14:55-65). This could support a narrower construction tied to the specific embodiment disclosed.
VI. Other Allegations
- Indirect Infringement: The complaint alleges active inducement by "intentionally aiding and abetting third parties' use and/or sale of chipsets" and contributory infringement by selling chipsets that are a "material part of the invention" (Compl. ¶13-14, ¶18-19). No specific facts, such as references to user manuals or technical documentation, are provided to support intent.
- Willful Infringement: The complaint alleges that nVidia had "actual notice" of the patents and infringed with knowledge of OPTi's rights, rendering the infringement "willful and deliberate" (Compl. ¶15, ¶20). The complaint does not allege any specific facts to support this assertion, such as the sending of a pre-suit notice letter.
VII. Analyst’s Conclusion: Key Questions for the Case
- A central evidentiary question will be one of operational equivalence: what proof will be offered to show that the internal hardware logic of the nVidia nForce chipsets performs the precise, predictive snooping method claimed in the '906 and '036 patents, particularly concerning the specific timing of the "next-line inquiry" relative to the ongoing data transfer?
- A key legal issue will be one of claim scope: given the detailed description's focus on Pentium-era processors and the PCI bus protocol, can the asserted claims be construed to cover subsequent or different bus architectures and processor interactions implemented in the accused nForce products, or are they limited to the specific technical environment disclosed in the patents?
- A third question will relate to the "Compact ISA-bus" patents: does the accused bus interface on the nForce chipsets, which may be compliant with other standards (e.g., HyperTransport), nonetheless embody the specific multiplexed signaling structure claimed in the '807 and '141 patents?