2:14-cv-00199
DSS Technology Management Inc v. Taiwan Semiconductor Mfg Co Ltd
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: DSS Technology Management, Inc. (Texas)
- Defendants: Taiwan Semiconductor Manufacturing Company, Limited (Taiwan); Samsung Electronics Co., Ltd. (Korea); NEC Corporation of America (Nevada) (and their various U.S. subsidiaries)
- Plaintiff’s Counsel: Nix Patterson & Roach, L.L.P.
- Case Identification: 2:14-cv-00199, E.D. Tex., 03/10/2014
- Venue Allegations: Venue is alleged based on Defendants conducting business in the district, including the sale and importation of products manufactured by the accused processes, and one Defendant subsidiary (Samsung Telecommunications America L.L.C.) having its principal place of business within the district.
- Core Dispute: Plaintiff alleges that semiconductor chips manufactured by Defendants using their 28-nanometer node processes are made by a method that infringes a patent on reduced-pitch lithography.
- Technical Context: The lawsuit concerns advanced semiconductor manufacturing, specifically double-patterning lithography, a technique used to create smaller, denser features on integrated circuits than is possible with a single exposure, enabling more powerful and efficient processors.
- Key Procedural History: While not mentioned in the complaint, the provided patent documents include an Inter Partes Review (IPR) Certificate issued on February 1, 2018. This certificate, resulting from IPRs filed by third parties after the complaint, confirms the cancellation of claims 1-12, 15, and 16 of the asserted patent. As the complaint’s allegations focus on claim 1, the subsequent cancellation of all asserted claims presents a fundamental challenge to the continuation of the case.
Case Timeline
| Date | Event |
|---|---|
| 1994-12-22 | Earliest Priority Date ('084 Patent) |
| 1997-07-29 | Issue Date, U.S. Patent No. 5,652,084 |
| 2014-03-10 | Complaint Filing Date |
| 2014-06-24 | Inter Partes Review (IPR2014-01030) Filed |
| 2014-09-12 | Inter Partes Review (IPR2014-01493) Filed |
| 2018-02-01 | IPR Certificate Issued, Cancelling Claims 1-12, 15, 16 |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 5,652,084 - “Method for Reduced Pitch Lithography” (Issued July 29, 1997)
The Invention Explained
- Problem Addressed: The patent addresses the physical limitations of photolithography in semiconductor manufacturing, where the minimum resolution of the optical equipment determines the minimal "pitch," or spacing, between features on a chip, thereby limiting device density (Compl. ¶23; ’084 Patent, col. 1:28-35).
- The Patented Solution: The invention proposes a multi-step, double-patterning method. A first layer of photoresist is applied and patterned using a first mask. This initial pattern is then "stabilized"—for example, through a chemical or thermal treatment—to make it durable. A second layer of photoresist is then applied over the stabilized first pattern and patterned using a second mask. This sequence creates a final, combined pattern with features that are closer together than could be achieved in a single lithographic exposure step (’084 Patent, Abstract; col. 2:46-56). The process flow is illustrated in FIG. 1, with the "stabilize first patterned layer" step being a critical intermediate action (’084 Patent, col. 4:30-34).
- Technical Importance: This pitch-splitting technique allows for the fabrication of circuit features smaller than the wavelength of light used in the lithography tool, a key innovation for continuing the trend of semiconductor scaling (’084 Patent, col. 12:30-39).
Key Claims at a Glance
- The complaint asserts "at least claim 1" and reserves the right to assert other claims (Compl. ¶37, ¶41, ¶44).
- Independent Claim 1 is a method claim requiring the following sequential steps:
- (a) forming a first imaging layer over the semiconductor wafer;
- (b) patterning the first imaging layer in accordance with a first pattern to form a first patterned layer having a first feature;
- (c) stabilizing the first patterned layer;
- (d) forming a second imaging layer over the first pattern layer; and
- (e) patterning the second imaging layer in accordance with a second pattern to form a second patterned layer having a second feature, where the combined features are "formed relatively closer to one another than is possible through a single exposure to radiation." (’084 Patent, col. 13:5-24).
III. The Accused Instrumentality
Product Identification
The accused instrumentalities are the semiconductor manufacturing methods used by Defendants, specifically their "28 nanometer node processes" (Compl. ¶6, ¶15). Products identified as being manufactured by these alleged processes include the Cyclone V SoCS, Snapdragon 600 and 800 processors, and the Exynos 5140 processor (Compl. ¶6, ¶8, ¶15).
Functionality and Market Context
The complaint alleges these are advanced lithography processes for fabricating high-performance semiconductors (Compl. ¶37). The named processors power a wide range of consumer electronics, and the complaint positions the Defendants as major suppliers in the global semiconductor market, thereby suggesting the commercial significance of the accused manufacturing methods (Compl. ¶6, ¶15, ¶46). The complaint does not provide specific technical details about how the accused 28nm processes operate.
No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint does not provide a detailed claim chart or specific factual allegations mapping the accused processes to the claim elements. It asserts infringement in a conclusory manner, stating that the accused products are "made by the lithography processes disclosed" in the patent (Compl. ¶37). The following chart summarizes this general allegation against the elements of claim 1.
’084 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| (a) forming a first imaging layer over the semiconductor wafer; | The complaint alleges that Defendants' 28nm manufacturing processes involve lithography. No specific details on the formation of a first imaging layer are provided. | ¶6, ¶37 | col. 3:24-30 |
| (b) patterning the first imaging layer in accordance with a first pattern to form a first patterned layer having a first feature; | The complaint alleges that Defendants' 28nm manufacturing processes involve lithography. No specific details on the patterning of a first layer are provided. | ¶6, ¶37 | col. 4:6-12 |
| (c) stabilizing the first patterned layer; | The complaint does not provide specific allegations regarding a distinct stabilization step, alleging generally that the accused processes are those disclosed in the patent. | ¶37 | col. 4:30-34 |
| (d) forming a second imaging layer over the first pattern layer; and | The complaint does not provide specific allegations regarding the formation of a separate, second imaging layer. | ¶37 | col. 5:58-64 |
| (e) patterning the second imaging layer in accordance with a second pattern to form a second patterned layer... | The complaint does not provide specific allegations regarding the patterning of a second layer to achieve reduced pitch. | ¶37 | col. 6:11-17 |
Identified Points of Contention
- Evidentiary Question: The complaint's lack of technical detail raises the question of what evidence Plaintiff will be able to produce from discovery to demonstrate that Defendants' proprietary 28nm processes practice every step of Claim 1, including the separate formation of two imaging layers and, crucially, a distinct "stabilizing" step between the two patterning events.
- Technical Question: A key factual dispute may be whether the accused processes use two separate, physically distinct imaging layers as recited in Claim 1, or if they employ an alternative double-patterning technique, such as the single-layer, dual-exposure method also described as an alternative embodiment in the ’084 Patent’s specification (e.g., FIG. 6).
V. Key Claim Terms for Construction
The Term: "stabilizing the first patterned layer"
Context and Importance: This term recites the central, inventive concept that distinguishes the claimed method from a simple sequence of two unrelated patterning steps. The construction of "stabilizing" will be critical to the scope of the claim and, therefore, the infringement analysis. Practitioners may focus on this term because its definition will determine whether any intermediate hardening of a photoresist layer meets the limitation, or if a more specific, deliberate treatment is required.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states that "Any suitable stabilization technique may be used" (’084 Patent, col. 4:31-32), which could support an argument that the term should not be confined to the specific examples provided.
- Evidence for a Narrower Interpretation: The patent describes specific embodiments in detail, such as a "deep ultraviolet (DUV) stabilization technique" that involves irradiating the layer while heating it to approximately 230 degrees Celsius (’084 Patent, col. 4:45-54). A defendant could argue these examples define and limit the scope of what "stabilizing" means in the context of the invention.
The Term: "forming a second imaging layer over the first pattern layer"
Context and Importance: This language is central to the structure of the claimed method. Infringement under Claim 1 requires proof that a second, distinct layer is formed, as opposed to re-exposing the original layer. The interpretation of "forming a second... layer" will differentiate this claim from other double-patterning methods.
Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term "over" is general and could be argued to encompass various methods of applying a subsequent material that results in a multi-level structure.
- Evidence for a Narrower Interpretation: The patent’s description and figures (e.g., FIG. 4) show the second imaging layer (240) formed to "surround" the first patterned layer (232) and cover the underlying substrate (’084 Patent, col. 5:58-62). This could support a narrower construction requiring a distinct material deposition step that creates a new, separate layer, rather than a modification of the first.
VI. Other Allegations
Indirect Infringement
The complaint alleges inducement of infringement, asserting that Defendants like TSMC make infringing semiconductors with the knowledge that their customers will import and sell products containing them in the U.S. (Compl. ¶35, ¶38). The basis for intent is alleged as actively marketing and encouraging the sale and use of products containing the accused semiconductors (Compl. ¶38).
Willful Infringement
The complaint alleges that "At least as to the time of this filing, TSMC knew of the '084 Patent," and that Defendants knew or should have known their actions would result in infringement, forming the basis for a willfulness claim (Compl. ¶38, ¶45, ¶51).
VII. Analyst’s Conclusion: Key Questions for the Case
An Evidentiary Hurdle: A primary question is evidentiary. Can the Plaintiff, through discovery, uncover evidence that the Defendants' highly proprietary and complex 28nm manufacturing processes map directly onto the specific, multi-step sequence recited in Claim 1, especially given the complaint’s initial lack of technical specifics?
A Definitional Dispute: The case would likely involve a critical claim construction dispute over the scope of "stabilizing." The outcome will depend on whether this term is construed broadly to cover any intermediate process that hardens a patterned layer, or narrowly to the specific DUV and thermal treatments detailed in the patent's embodiments.
A Question of Mootness: The most significant question impacting the litigation is one of patent viability. Given that all asserted claims were cancelled in IPR proceedings initiated after the complaint was filed, the fundamental basis for the infringement action appears to be moot, raising the dispositive issue of whether any valid intellectual property right remains to be litigated.