DCT

2:16-cv-00693

Alacritech Inc v. CenturyLink Inc

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Key Events
Complaint

I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:16-cv-00693, E.D. Tex., 06/30/2016
  • Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because CenturyLink is subject to personal jurisdiction, regularly conducts business in the district, including operating two data centers in Dallas, and has committed acts of infringement within the district.
  • Core Dispute: Plaintiff alleges that Defendant’s data center operations and associated cloud and hosting services infringe eight patents related to network acceleration technologies that offload protocol processing from a host computer's CPU to a network interface device.
  • Technical Context: The technology concerns methods for improving server and network efficiency by using dedicated hardware on network interface devices to handle tasks typically performed by a host CPU, such as processing TCP/IP protocol layers.
  • Key Procedural History: The complaint does not mention any significant prior litigation, licensing history, or post-grant proceedings concerning the asserted patents.

Case Timeline

Date Event
1997-10-14 Earliest Priority Date for Asserted Patents
2006-10-17 U.S. Patent No. 7,124,205 Issues
2007-06-26 U.S. Patent No. 7,237,036 Issues
2008-02-26 U.S. Patent No. 7,337,241 Issues
2010-03-02 U.S. Patent No. 7,673,072 Issues
2011-05-17 U.S. Patent No. 7,945,699 Issues
2012-03-06 U.S. Patent No. 8,131,880 Issues
2014-08-12 U.S. Patent No. 8,805,948 Issues
2015-06-09 U.S. Patent No. 9,055,104 Issues
2016-06-30 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,124,205 - *Network Interface Device that Fast-Path Processes Solicited Session Layer Read Commands*

  • Patent Identification: U.S. Patent No. 7,124,205, issued October 17, 2006.

The Invention Explained

  • Problem Addressed: Conventional network data processing consumes a significant portion of a host computer's CPU power, as the CPU must process network messages layer-by-layer through a protocol stack (e.g., TCP/IP). This creates bottlenecks, particularly in network-attached storage (NAS) and storage area network (SAN) environments ( Compl. ¶16; ’205 Patent, col. 1:40-54).
  • The Patented Solution: The invention provides a network interface device (NID) that accelerates data transfers by using a dedicated "fast-path" to process certain network communications, thereby bypassing the host computer's protocol stack. For data transfers handled by the fast-path, the host CPU performs no network or transport layer processing. Other communications, or those with errors, are handled by the host CPU in a conventional "slow-path." The patent specifically addresses applying this fast-path to responses for solicited session layer read commands, such as iSCSI (’205 Patent, Abstract; col. 3:40-67).
  • Technical Importance: This dual-path approach aimed to reduce the processing burden on host CPUs in high-traffic data storage environments, increasing the speed and efficiency of data transfers without sacrificing the flexibility needed to handle complex protocols or exceptions (Compl. ¶10, ¶18).

Key Claims at a Glance

  • The complaint asserts exemplary claim 5, which depends on independent claim 1 (Compl. ¶35).
  • Essential elements of independent claim 1 (an apparatus claim) include:
    • A host computer with a protocol stack (including a session layer portion) and a destination memory.
    • A network interface device (NID) coupled to the host computer.
    • The NID receiving a response to a solicited read command of the session layer protocol.
    • The NID performing "fast-path processing" on the response, placing a data portion into the destination memory "without the protocol stack of the host computer performing any network layer processing or any transport layer processing on the response."
  • The complaint does not explicitly reserve the right to assert dependent claims for this patent but makes a general reservation (Compl. ¶34).

U.S. Patent No. 7,237,036 - *Fast-Path Apparatus for Receiving Data Corresponding a TCP Connection*

  • Patent Identification: U.S. Patent No. 7,237,036, issued June 26, 2007.

The Invention Explained

  • Problem Addressed: The patent's background describes the inefficiency of conventional, layer-by-layer software processing of network protocol stacks, which consumes host CPU cycles and memory bandwidth, thereby diminishing the ability of servers to perform other tasks (’036 Patent, col. 2:1-24).
  • The Patented Solution: The invention is a communication processing device that "collapses" the protocol stack into a single, wider layer. This device can intelligently choose whether a received data packet should be processed on a "fast-path" directly to a destination in host memory or on a "slow-path" involving the host's processor. The device itself contains a processor for handling the fast-path processing, including updating TCP state information (’036 Patent, Abstract; col. 5:10-44).
  • Technical Importance: This architecture sought to offload the majority of network data processing to dedicated hardware, freeing the host CPU for application-level tasks and accelerating data throughput in servers (Compl. ¶19).

Key Claims at a Glance

  • The complaint asserts exemplary claim 1 (Compl. ¶48).
  • Essential elements of independent claim 1 (a device claim) include:
    • A communication processing mechanism connected to a first processor (the host CPU).
    • This mechanism contains a second processor running instructions to process a message packet.
    • The context of the communication (e.g., MAC address, IP address, TCP state) is used to transfer data from the packet to the host's memory.
    • The TCP state information is updated by the second processor.
  • The complaint reserves the right to identify additional infringing claims (Compl. ¶47).

Multi-Patent Capsules

  • U.S. Patent No. 7,337,241: Titled Fast-Path Apparatus for Receiving Data Corresponding to a TCP Connection, issued February 26, 2008. This patent describes a method where a "second processor" (on an interface device) segments data for transmission, prepends multi-layer packet headers, and transmits the resulting packets. The device can also receive packets and, based on certain criteria, select whether the packet is processed by the first processor (host CPU) or the second processor (the interface device) (’241 Patent, Abstract). The complaint asserts exemplary claim 16 (dependent on claim 9) and alleges infringement by Large Segment Offload (LSO) and Receive Side Coalescing (RSC) functionality in CenturyLink's data centers (Compl. ¶59-60).

  • U.S. Patent No. 7,673,072: Titled Fast-Path Apparatus for Transmitting Data Corresponding to a TCP Connection, issued March 2, 2010. This patent discloses a method where a computer establishes a TCP connection context and transfers it to an interface device. The interface device then uses this context to divide data into segments and create and prepend headers to form transmit packets, offloading this work from the host (’072 Patent, Abstract). The complaint asserts exemplary claim 16 (dependent on claim 15) and accuses LSO functionality in CenturyLink's data centers of infringement (Compl. ¶72-73).

  • U.S. Patent No. 7,945,699: Titled Obtaining a Destination Address so that a Network Interface Device Can Write Network Data without Headers Directly into Host Memory, issued May 17, 2011. This patent describes a method where a network interface receives packets, obtains a destination memory address from the host computer for an application running above the transport layer, and then transfers the data portion of the packets to that destination without the network or transport layer headers (’699 Patent, Abstract). The complaint asserts exemplary claim 1 and accuses products supporting InfiniBand and/or RoCE protocols of infringement (Compl. ¶85-86).

  • U.S. Patent No. 8,131,880: Titled Intelligent Network Interface Device and System for Accelerated Communication, issued March 6, 2012. This patent details a method for transferring a received packet to a host, where a communication device parses the packet header to determine if it conforms to TCP, generates a flow key to identify the communication flow, and associates an operation code indicating the packet's status (e.g., whether it is a candidate for bypassing host processing) (’880 Patent, Abstract). The complaint asserts exemplary claim 1 and accuses RSC functionality in the accused products of infringement (Compl. ¶98-99).

  • U.S. Patent No. 8,805,948: Titled Intelligent Network Interface System and Method for Protocol Processing, issued August 12, 2014. This patent describes an apparatus where a network interface parses received packet headers to identify the TCP connection and check for exception conditions (e.g., fragmentation, FIN flag). Packets without exceptions have their headers removed and payloads stored directly in a host buffer, while packets with exceptions are directed to the host's protocol stack for processing (’948 Patent, Abstract). The complaint asserts exemplary claim 17 and accuses RSC functionality of infringement (Compl. ¶111-112).

  • U.S. Patent No. 9,055,104: Titled Freeing Transit Memory on a Network Interface Device prior to Receiving an Acknowledgement that Transmit Data Has Been Received by a Remote Device, issued June 9, 2015. This patent discloses a method where a network interface device sends a response to the host computer indicating that data has been transmitted before it receives a network-level acknowledgement (ACK) that the data was received by the remote device. This allows the host to free up resources associated with the transmission command earlier than in a conventional system (’104 Patent, Abstract). The complaint asserts exemplary claim 1 and accuses LSO functionality of infringement (Compl. ¶124-125).

III. The Accused Instrumentality

Product Identification

The accused instrumentalities are CenturyLink's data center operations and the associated products and services it provides to customers, including cloud services, colocation services, storage services, and managed hosting (Compl. ¶27-28). The complaint alleges these services are implemented using servers and network devices, such as the Dell PowerEdge C6320 Rack Server, which incorporates network controllers like the Intel 82599 10GbE Controller (Compl. ¶35, ¶48).

Functionality and Market Context

The complaint alleges that the accused servers and network devices implement network and storage acceleration technologies, including Receive Segment Coalescing (RSC), Large Segment Offload (LSO), TCP Offload Engine (TOE), and protocols that use Remote Direct Memory Access (RDMA), such as InfiniBand and RoCE (Compl. ¶24, ¶34). These technologies are designed to offload packet processing tasks from the server's main CPU to the network controller's hardware, reducing CPU utilization and increasing data throughput (Compl. ¶13, ¶19). A screenshot provided in the complaint from a Microsoft technical document describes RSC as a stateless offload technology that reduces CPU utilization by having a capable network adapter parse multiple TCP/IP packets, strip their headers, and join the payloads into a single larger packet for delivery to the network stack (Compl. ¶35, p. 13). The complaint asserts that a "large and growing portion of CenturyLink's revenue is tied to the infringing data centers" and that these technologies are critical to their performance (Compl. ¶30).

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,124,205 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
An apparatus comprising: a host computer having a protocol stack and a destination memory, the protocol stack including a session layer portion, the session layer portion being for processing a session layer protocol; CenturyLink uses servers (e.g., Dell PowerEdge C6320) that comprise a host computer with destination memory and a protocol stack (e.g., from its Windows or Linux OS) that processes session layer protocols like iSCSI. ¶35 col. 3:40-44
and a network interface device coupled to the host computer, The Dell C6320 server includes a network interface device, such as an Intel 82599 10GbE controller, which is coupled to the host computer. ¶35 col. 3:45-46
the network interface device receiving from outside the apparatus a response to a solicited read command, the solicited read command being of the session layer protocol, The network interface device receives responses to solicited read commands of the session layer protocol (e.g., iSCSI) from outside the server. ¶35 col. 3:47-50
performing fast-path processing on the response such that a data portion of the response is placed into the destination memory without the protocol stack of the host computer performing any network layer processing or any transport layer processing on the response. The network interface device performs Receive Segment Coalescing (RSC), which allegedly constitutes fast-path processing by coalescing incoming packets and placing the combined data into destination memory, bypassing network and transport layer processing by the host computer's protocol stack. ¶35 col. 3:51-57

U.S. Patent No. 7,237,036 Infringement Allegations

Claim Element (from Independent Claim 1) Alleged Infringing Functionality Complaint Citation Patent Citation
A device for use with a first apparatus that is connectable to a second apparatus, the first apparatus containing a memory and a first processor operating a stack of protocol processing layers that create a context for communication... The Intel 82599 controller is a device for use with a first apparatus (the Dell C6320 server). The server contains memory and a first processor (e.g., Intel Xeon) running a protocol stack that creates a communication context including MAC address, IP address, and TCP state. ¶48 col. 1:15-24
a communication processing mechanism connected to the first processor, said communication processing mechanism containing a second processor running instructions to process a message packet such that the context is employed to transfer data contained in said packet to the first apparatus memory The Intel 82599 controller is a communication processing mechanism connected to the server's processor and contains a second processor. It allegedly runs instructions to process incoming packets using RSC, employing the communication context to transfer data to the server's memory. ¶48 col. 1:25-32
and the TCP state information is updated by said second processor. The second processor of the Intel 82599 controller allegedly updates TCP state information, for example by posting a coalesced header with updated TCP state information. ¶48 col. 1:33-34

Identified Points of Contention

  • Scope Questions: A central dispute for the '205 Patent may be whether the accused RSC functionality constitutes "fast-path processing... without the protocol stack of the host computer performing any network layer processing or any transport layer processing." The complaint alleges this bypass occurs, but defendants may argue that RSC technology inherently relies on and interacts with the host's driver and protocol stack, thus not meeting the "without" limitation. For the '036 Patent, a question is whether the hardware logic on the Intel 82599 controller qualifies as a "second processor running instructions" as distinct from the host's "first processor," or if it is better characterized as a fixed-function hardware accelerator that does not "run instructions" in the manner contemplated by the patent.
  • Technical Questions: A key evidentiary question across multiple patents will be the precise division of labor between the host CPU/OS and the accused network controllers. For instance, what specific processing steps for coalescing packets (RSC) or segmenting packets (LSO) are performed exclusively by the controller's hardware, and what steps still require management or execution by the host's protocol stack software? The complaint includes a flowchart, Figure 7-43, illustrating the decision logic for RSC processing, which distinguishes between a "Coalescing Flow" (the alleged fast-path) and a "No Coalescing Flow" (the slow-path), raising the factual question of which path the accused products take under normal operating conditions and whether that path maps to the claims (Compl. ¶35, p. 17).

V. Key Claim Terms for Construction

  • For U.S. Patent No. 7,124,205:

    • The Term: "without the protocol stack of the host computer performing any network layer processing or any transport layer processing"
    • Context and Importance: This negative limitation is the core of the infringement theory for the '205 Patent. The viability of the claim against modern offload engines like RSC will depend on whether they are found to operate completely independently of the host's network and transport protocol stack layers. Practitioners may focus on this term because standard network drivers and hardware offload features often cooperate closely with the host OS, creating a factual and legal dispute over whether any processing is "performed by" the stack.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification's general description of the problem focuses on avoiding "brute-force, layer-by-layer processing" by the host's CPU, which could suggest the claim is meant to cover any system that avoids this specific, burdensome sequence, even if some coordination with the stack remains (Compl. ¶16).
      • Evidence for a Narrower Interpretation: The patent's abstract states that for fast-path transfers, "the protocol stack of the host performs no network layer or transport layer processing" ('205 Patent, Abstract). This explicit and absolute language may support a narrow construction requiring complete bypass of those layers, potentially excluding technologies that still rely on the host stack for setup, context, or error handling.

  • For U.S. Patent No. 7,237,036:

    • The Term: "a second processor running instructions"
    • Context and Importance: The infringement allegation identifies the Intel 82599 controller's hardware as this "second processor." The case may turn on whether this controller, which includes specialized hardware for packet processing, is considered a "processor" that "runs instructions" in the sense used by the patent, or merely a fixed-function ASIC.
    • Intrinsic Evidence for Interpretation:
      • Evidence for a Broader Interpretation: The specification describes the "communication processing device" in general terms as having "specialized hardware circuits that are much faster at their specific tasks than a general purpose CPU," which could encompass the logic on the Intel 82599 controller (’036 Patent, Abstract).
      • Evidence for a Narrower Interpretation: The detailed description in the patent family often refers to a "pipelined trio of specialized microprocessors" designed for protocol processing (’036 Patent, col. 7:13-16). This may suggest that the claimed "second processor" is not merely any hardware logic but a programmable, instruction-based microprocessor, potentially distinguishing it from the accused controller.

VI. Other Allegations

  • Indirect Infringement: The complaint alleges both induced and contributory infringement for all asserted patents. The inducement theory is based on CenturyLink providing data center services and equipment to customers and "encouraging and facilitating" them to use the infringing functionality (e.g., RSC, LSO) (Compl. ¶38, ¶50). The contributory infringement theory alleges that the specialized hardware and software components that perform these functions are not staple articles of commerce suitable for substantial non-infringing use and are a material part of the patented inventions (Compl. ¶39, ¶51).
  • Willful Infringement: The complaint does not use the term "willful." However, for each patent, it alleges that CenturyLink has "actual knowledge" of Alacritech's rights and the alleged infringement "based on at least the filing and service of this Complaint" (Compl. ¶37, ¶49). This allegation appears to be aimed at establishing a basis for enhanced damages based on post-suit conduct.

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of functional operation: do commercially standard offload technologies like RSC and LSO, as implemented in the accused data centers, operate in a manner that fully satisfies the specific "fast-path" requirements of the asserted patents? This will likely involve a detailed technical comparison between how the accused systems divide processing tasks and the patents' descriptions of bypassing the host's protocol stack.
  • A second key question will be one of definitional scope: can claim terms rooted in the patents' specific architecture, such as "fast-path processing... without" host stack involvement ('205 Patent) and a "second processor running instructions" ('036 Patent), be construed broadly enough to read on the functionality of industry-standard network controllers, or are they limited by the specification to the more specialized, fully-offloaded co-processing systems described in the patents' embodiments?