DCT
2:17-cv-00110
Janus Semiconductor Research LLC v. Kingston Technology Co Inc
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Janus Semiconductor Research, LLC (Texas)
- Defendant: Kingston Technology Company, Inc. (Delaware)
- Plaintiff’s Counsel: THE DAVIS FIRM, PC; Olavi Dunne LLP
- Case Identification: 2:17-cv-00110, E.D. Tex., 02/03/2017
- Venue Allegations: Plaintiff alleges venue is proper because Defendant has transacted business and committed acts of direct and indirect infringement in the Eastern District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s DDR3 and DDR4 SDRAM memory products infringe a patent related to a distributed, self-timed, and self-enabled clocking system for digital circuits.
- Technical Context: The technology concerns methods for managing clock signals in complex integrated circuits to improve performance and power efficiency, a critical function in modern electronics like high-speed memory modules.
- Key Procedural History: The complaint does not mention any prior litigation, licensing history, or inter partes review proceedings involving the patent-in-suit. It does note that the patent has been cited as relevant prior art in at least 94 subsequent U.S. patents and applications.
Case Timeline
| Date | Event |
|---|---|
| 1997-09-19 | ’620 Patent Priority Date |
| 1999-11-16 | ’620 Patent Issue Date |
| 2000-06-01 | JEDEC releases first DDR SDRAM specification |
| 2017-02-03 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 5,987,620 - "Method and Apparatus for a Self-Timed and Self-Enabled Distributed Clock," Issued November 16, 1999
The Invention Explained
- Problem Addressed: At the time of the invention, traditional synchronous clock designs in complex microprocessors faced increasing problems with clock skew (timing differences across a chip), power consumption, and electronic noise, which limited performance. (’620 Patent, col. 2:2-15). Alternative asynchronous designs solved these issues but introduced their own challenges related to verification and predictable operation. (’620 Patent, col. 2:16-31; Compl. ¶40).
- The Patented Solution: The patent describes a hybrid approach using a "distributed self-timed and self-enabled clock." Instead of one central clock, individual functional units within a processor (e.g., a decode unit or an execution unit) are given their own local clock module, or "self-clock." (’620 Patent, Fig. 1). These self-clocks are "self-enabled," meaning they are activated only when there is valid data to process, and "self-timed," meaning they generate their own timing pulses. This architecture aims to combine the low-power advantages of asynchronous systems with the verifiable, predictable behavior of synchronous ones. (’620 Patent, Abstract; col. 3:1-13).
- Technical Importance: This design sought to enable higher processor frequencies and improve instruction-per-cycle performance by mitigating the physical limitations of centralized clock distribution while maintaining deterministic behavior for verification. (’620 Patent, col. 4:30-40).
Key Claims at a Glance
- The complaint asserts "one or more claims of the ’620 patent, including at least claim 1." (Compl. ¶57). The infringement analysis focuses exclusively on claim 1.
- Independent Claim 1 of the ’620 patent recites:
- A control circuit that detects input clock pulses and provides an enable signal while the input clock pulses are provided;
- A clock delay device coupled to the control circuit, which has inputs for a feedback clock, an input clock, and an enable signal, and provides an output clock pulse when enabled; and
- Wherein the clock delay device, when enabled, provides output clock pulses that are synchronized with the input clock pulses.
- The complaint notes that the patent’s four independent claims (1, 16, 33, and 46) generally recite either a clock system or functional blocks that include such a system. (Compl. ¶41).
III. The Accused Instrumentality
Product Identification
- The accused products are Kingston’s DDR3 and DDR4 SDRAM memory products, including the ValueRAM, Kingston-branded, and HyperX product lines (e.g., FURY, Savage, Predator). (Compl. ¶48).
Functionality and Market Context
- The complaint alleges these products conform to JEDEC industry standards for DDR3 and DDR4 memory. (Compl. ¶48). The core accused functionality is the Delay-Locked Loop (DLL) circuit present in these memory modules. (Compl. ¶49). The complaint alleges the DLL is used to generate an internal clock and synchronize the memory's operation, for example, by aligning the data output signal with the external clock signal. (Compl. ¶¶49, 56). The complaint references the JEDEC DDR3 SDRAM standard to describe the operation of the accused DLLs, including how they are enabled and disabled via a Mode Register (MR1). (Compl. ¶¶49, 51). The complaint includes an image from the JEDEC standard defining the MR1 register, which contains a bit to enable or disable the DLL. (Compl. ¶49, Fig. 10).
IV. Analysis of Infringement Allegations
’620 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a control circuit that detects input clock pulses and that provides an enable signal while the input clock pulses are provided | The accused products allegedly have a control circuit that detects external clock pulses at the CK input and provides an enable signal for the DLL based on settings stored in Mode Register MR1. | ¶¶50, 51 | col. 15:7-13 |
| a clock delay device, coupled to the control circuit, that has a plurality of inputs and an output that provides an output clock pulse | The DLL in the accused products is alleged to be the "clock delay device." It allegedly has multiple inputs and provides an output clock pulse when enabled. The complaint provides a diagram of a typical DLL to illustrate its structure. (Compl. ¶52). | ¶52 | col. 11:39-56 |
| the inputs including: a feedback clock input that is coupled to the output of the clock delay device | The DLL in the accused products allegedly includes a feedback loop where the DLL's output is fed back as an input to adjust the timing. A timing diagram is provided to show this operation. (Compl. ¶53). | ¶53 | col. 11:43-44 |
| a clock input for receiving the input clock pulses | The DLL in the accused products allegedly has a clock input (CK) for receiving external clock pulses. | ¶54 | col. 11:43-44 |
| an enable input that receives the enable signal to enable the clock delay device | The DLL allegedly includes an enable input that receives an enable signal based on the settings in Mode Register MR1. | ¶55 | col. 11:43-44 |
| wherein the clock delay device, when enabled by the enable signal, provides output clock pulses that are synchronized with the input clock pulses | When enabled, the DLL allegedly provides output clock pulses that are synchronized with the input clock pulses to ensure the memory's output data signal is aligned with the input clock signal. | ¶56 | col. 12:28-34 |
- Identified Points of Contention:
- Scope Questions: The patent specification repeatedly describes the invention in the context of a "pipeline processor" and its internal "functional blocks" like a decode unit or an execute unit. (’620 Patent, Abstract, Fig. 1). A primary question for the court will be whether the claims, interpreted in light of this specification, can read on a Delay-Locked Loop (DLL) circuit within a separate SDRAM memory module, or if their scope is limited to the internal architecture of a microprocessor.
- Technical Questions: A key technical question is whether the "enable/disable" functionality of a standard JEDEC-compliant DLL, which is set via a configuration bit in a mode register (MR1), performs the same function as the "self-enabled" clock described in the patent. The patent links the enabling of its "self-clock" to the dynamic presence of valid data in a pipeline to reduce power. (’620 Patent, col. 3:23-29). The infringement allegation, however, relies on a more static configuration setting. The complaint includes a diagram from a patent figure to show how its invented functional blocks process data using local self-clocks. (Compl. ¶43).
V. Key Claim Terms for Construction
The Term: "control circuit"
- Context and Importance: This term is central to the infringement theory. Plaintiff alleges that the circuitry in the accused memory modules that reads the MR1 register and enables or disables the DLL constitutes the claimed "control circuit." Practitioners may focus on this term because its construction will determine whether a static configuration mechanism can meet a claim limitation that the patent specification appears to describe as a dynamic, data-dependent control system.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The claim language itself does not explicitly require the "enable signal" to be tied to the processing of valid data, only that it is provided "while the input clock pulses are provided."
- Evidence for a Narrower Interpretation: The specification describes the control logic (e.g., control block 101 in Fig. 4) as being responsible for enabling the self-clock based on the presence of valid data and the absence of stall conditions, suggesting a more complex and dynamic function than setting a single mode bit. (’620 Patent, col. 15:7-21).
The Term: "self-timed and self-enabled clock circuit" (from the preamble of Claim 1)
- Context and Importance: This phrase, taken from the patent's title, describes the core of the invention. Its construction will be critical, especially regarding whether the preamble is ruled to be a claim limitation. Plaintiff's case depends on a standard DLL being considered a "self-timed and self-enabled clock circuit."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A DLL is a type of clock circuit that adjusts its own timing (self-timed, in a sense) and can be turned on or off (self-enabled). The claim body does not use the term "distributed," which is prominent in the specification.
- Evidence for a Narrower Interpretation: The patent's Abstract and Summary of the Invention consistently describe a "distributed" system where multiple, distinct functional units each have their own self-clock. The patent states the invention "is distributed to various parts of the design and pipeline stages, rather than a centralized clock." (’620 Patent, col. 3:9-13). This could support an argument that a single DLL in a memory module is not the "self-timed and self-enabled clock circuit" of the invention.
VI. Other Allegations
- Indirect Infringement: The complaint alleges induced infringement, stating that Kingston provides documentation and training materials that instruct customers to use the accused products in a way that infringes the ’620 patent. (Compl. ¶60).
- Willful Infringement: The complaint alleges willful infringement based on Kingston’s knowledge of the ’620 patent and its alleged infringement from "at least the date of service of this Complaint or shortly thereafter." (Compl. ¶59). No pre-suit knowledge is alleged.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: can the claims of the ’620 patent, which are described in the context of a microprocessor’s internal pipeline architecture, be construed to cover the function of a standard Delay-Locked Loop (DLL) circuit within a JEDEC-compliant SDRAM memory module?
- A key evidentiary question will be one of functional mapping: does the static "enable/disable" function of the accused DLLs, controlled by a mode register bit, meet the "self-enabled" limitation of Claim 1, which the patent specification repeatedly links to dynamic activation based on the flow of valid data through a processor pipeline?
- The case may also turn on a question of preamble construction: will the term "self-timed and self-enabled clock circuit" in the preamble be deemed a limitation on the claim, and if so, does the accused single DLL embody the specific distributed, power-saving architecture detailed in the patent's specification?