DCT

2:18-cv-00063

DIFF Scale Operation Research LLC v. Intel Corp

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I. Executive Summary and Procedural Information

  • Parties & Counsel:
  • Case Identification: 2:18-cv-00063, E.D. Tex., 03/08/2018
  • Venue Allegations: Plaintiff alleges venue is proper because Defendants are registered to do business in Texas, maintain offices and facilities within the Eastern District of Texas, and have committed the alleged acts of infringement in the district.
  • Core Dispute: Plaintiff alleges that Defendant’s Field-Programmable Gate Array (FPGA), networking, and Ethernet products infringe six patents related to semiconductor timing, clock recovery, and network traffic management technologies.
  • Technical Context: The technology concerns fundamental circuit-level techniques for maintaining precise timing signals and managing data flow in high-speed digital communication networks, which are critical functions for modern semiconductor and networking hardware.
  • Key Procedural History: The complaint states the asserted patent portfolio originated with ADC Telecommunications, was later acquired by CommScope, and was subsequently assigned to Plaintiff. The complaint also notes that a separate portfolio of ADC patents was sold to HTC for $75 million in 2011 and later asserted against Apple, suggesting a history of valuation and assertion for the underlying technology portfolio.

Case Timeline

Date Event
1998-02-20 Priority Date for ’983 and ’166 Patents
1999-11-19 Priority Date for ’328 Patent
2001-03-02 Priority Date for ’413 and ’827 Patents
2001-04-10 ’166 Patent Issued
2001-08-03 Priority Date for ’758 Patent
2002-06-18 ’983 Patent Issued
2003-12-16 ’827 Patent Issued
2004-04-13 ’328 Patent Issued
2006-09-12 ’758 Patent Issued
2011-02-01 ’413 Patent Issued
2015-12-01 Intel acquires Altera Corporation
2018-03-08 Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,881,413 - Digital PLL With Conditional Holdover, Issued Feb. 1, 2011

The Invention Explained

  • Problem Addressed: In high-speed communication systems, timing signals must be maintained even if the primary reference clock signal is lost or degraded. If a system's Phase-Locked Loop (PLL) attempts to lock onto a degraded reference signal, it can introduce timing errors throughout the network. (’413 Patent, col. 2:4-17).
  • The Patented Solution: The invention proposes a "conditional holdover" method where the PLL monitors not just the presence of a reference clock signal, but also its quality via a "Synchronization Status Message" (SSM). If the SSM indicates the quality has dropped below a predetermined target level, the PLL enters a "holdover" state, generating its own stable timing signal and ignoring the degraded external reference, thereby preventing the propagation of timing errors. (’413 Patent, Abstract; col. 3:1-12).
  • Technical Importance: This approach allows a network element to make an intelligent, proactive decision about its timing source, improving network stability by rejecting low-quality signals rather than reacting only to a complete signal failure. (Compl. ¶34).

Key Claims at a Glance

  • The complaint asserts independent claim 21. (Compl. ¶97).
  • Claim 21 is a method claim with the following essential elements:
    • generating the timing signal from a reference clock signal in a phase locked loop;
    • monitoring a status message indicative of a quality level of the reference clock signal; and
    • placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,664,827 - Direct Digital Synthesizer Phase Locked Loop, Issued Dec. 16, 2003

The Invention Explained

  • Problem Addressed: Conventional PLLs can be disrupted by a sudden "step change" in the phase of an incoming reference clock, which can occur when a network switches between timing sources. A typical PLL will attempt to track this abrupt change, causing a temporary disruption in its output frequency until it re-locks. (’827 Patent, col. 1:19-23).
  • The Patented Solution: The invention describes a digital PLL that detects a step change in the phase difference between the reference and feedback signals. Upon detection, it "recenters" the digital phase comparator to mitigate the effect of the step change, preventing the disruption from propagating through the loop and affecting the output timing signal. The patent also describes using a processor to compensate for long-term oscillator drift. (’827 Patent, Abstract; col. 2:57-62).
  • Technical Importance: This method improves the stability of timing circuits by making them more robust against sudden phase changes in the reference clock, a common event in complex telecommunications networks with redundant timing sources. (Compl. ¶37).

Key Claims at a Glance

  • The complaint asserts independent claim 28. (Compl. ¶123).
  • Claim 28 is a machine-readable medium claim with instructions to perform a method comprising these essential elements:
    • sampling values of an error signal, where the error signal indicates a phase relationship between a reference clock signal and a feedback signal;
    • monitoring the sampled error signal values for a step change in the phase difference; and
    • recentering a phase comparator if a step change in the phase difference is detected.
  • The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,106,758 - Circuit and Method for Service Clock Recovery, Issued Sep. 12, 2006

  • Technology Synopsis: The patent addresses the problem of synchronizing a service clock at a destination node with a source node in a packet network. The solution involves using control values, calculated over a plurality of time periods, to set the frequency of a local service clock generated by a direct digital synthesis (DDS) circuit, thereby achieving adaptive clock recovery. (Compl. ¶¶44, 47-48).
  • Asserted Claims: At least claim 40 is asserted. (Compl. ¶148).
  • Accused Features: The complaint accuses Altera's single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) IP cores of incorporating infringing adaptive clock recovery functionality. (Compl. ¶132).

U.S. Patent No. 6,407,983 - Circuit and Method for Shaping Traffic in a Virtual Connection Network, Issued Jun. 18, 2002

  • Technology Synopsis: The patent describes an improved "traffic shaper" designed to deliver data packets from a source to a network at a substantially uniform rate, smoothing out "bursty" traffic. The system uses a counter and a request generator to distribute requests for transmission timeslots evenly over a measurement window, establishing a desired data rate. (Compl. ¶¶53-56).
  • Asserted Claims: At least claim 8 is asserted. (Compl. ¶168).
  • Accused Features: The complaint accuses Altera's network traffic shaping products, specifically the Altera TPX3103 and Altera TPX4004. (Compl. ¶158).

U.S. Patent No. 6,721,328 - Adaptive Clock Recovery for Circuit Emulation Service, Issued Apr. 13, 2004

  • Technology Synopsis: This patent discloses a method for adaptive clock recovery in a packet network. The system monitors the "relative maximum fill level" of a data buffer over a period of time and uses this peak value, rather than the instantaneous fill level, to control the frequency of the locally generated clock that reads data out of the buffer. (Compl. ¶¶63, 66).
  • Asserted Claims: At least claim 1 is asserted. (Compl. ¶190).
  • Accused Features: The complaint accuses Altera's single-clock FIFO (SCFIFO) and dual-clock FIFO (DCFIFO) IP cores of infringing. (Compl. ¶177).

U.S. Patent No. 6,216,166 - Shared Media Communications in a Virtual Connection Network, Issued Apr. 10, 2001

  • Technology Synopsis: The patent addresses efficient communications in a virtual connection network. The claimed system includes a "policing network element" that contains functionality for terminating a group of data that has a corrupted media access control (MAC) address, thereby preventing corrupted data from circulating improperly on the network. (Compl. ¶¶72, 76).
  • Asserted Claims: At least claim 1 is asserted. (Compl. ¶209).
  • Accused Features: The complaint accuses a wide range of Intel Ethernet Products, including Intel Ethernet Network Connections, Controllers, and PHYs. (Compl. ¶200).

III. The Accused Instrumentality

Product Identification

  • The complaint accuses multiple categories of Intel and Altera products. The primary accused instrumentalities for the lead patents are Intel's Field-Programmable Gate Array (FPGA) product families, including MAX, Arria, Stratix, and Cyclone series devices. (Compl. ¶¶83, 106). Other asserted patents target Altera's FIFO IP cores, traffic shaping products, and a broad range of Intel's Ethernet controllers and PHYs. (Compl. ¶¶132, 158, 177, 200).

Functionality and Market Context

  • The complaint alleges that the accused FPGAs incorporate infringing timing devices and PLLs that generate and manage timing signals. (Compl. ¶¶82, 85, 105, 108). FPGAs are programmable semiconductor devices central to numerous technology sectors, including data centers, telecommunications, and industrial systems. The internal timing and clock management circuitry, including PLLs, are fundamental to their operation. The allegations against other products relate to their roles in clock recovery, traffic management, and network policing. (Compl. ¶¶134, 160, 179, 202).

No probative visual evidence provided in complaint.

IV. Analysis of Infringement Allegations

U.S. Patent No. 7,881,413 Infringement Allegations

Claim Element (from Independent Claim 21) Alleged Infringing Functionality Complaint Citation Patent Citation
generating the timing signal from a reference clock signal in a phase locked loop The accused Intel ‘413 Products allegedly comprise a system for generating a timing signal from a reference clock signal in a phase locked loop. ¶93 col. 3:1-12
monitoring a status message indicative of a quality level of the reference clock signal The accused Intel ‘413 Products allegedly include functionality for monitoring a status message received from a source of the reference clock signal indicative of a quality level. ¶94 col. 3:55-67
placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level The accused Intel ‘413 Products allegedly contain functionality for placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level. ¶95 col. 4:47-52

U.S. Patent No. 6,664,827 Infringement Allegations

Claim Element (from Independent Claim 28) Alleged Infringing Functionality Complaint Citation Patent Citation
sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal The accused Intel ‘827 Products allegedly contain functionality for sampling an error signal indicative of a phase relationship between a reference clock signal and a feedback signal. ¶119 col. 2:57-62
monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal The accused Intel ‘827 Products allegedly comprise a system for monitoring sampled error signal values for a step change in the phase difference between the reference clock signal and feedback signal. ¶121 col. 8:1-14
and recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected The accused Intel ‘827 Products allegedly include functionality for recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected. ¶122 col. 8:40-44

Identified Points of Contention

  • Evidentiary Questions: The complaint's infringement allegations are made "on information and belief" and largely track the language of the claims. A central point of contention may be the factual and evidentiary basis for these allegations. The analysis will question what specific technical evidence demonstrates that the internal, complex circuitry of Intel's FPGAs performs the precise steps required by the claims.
  • Scope Questions (’413 Patent): The infringement theory for the ’413 Patent hinges on the accused products "monitoring a status message." The analysis raises the question of whether the internal signals within an FPGA can be construed as a "status message" as that term is used in the patent, which provides context from telecommunication standards like SONET/SDH. (’413 Patent, col. 2:35-55).
  • Technical Questions (’827 Patent): The infringement theory for the ’827 Patent requires "recentering a phase comparator" upon detecting a step change. The analysis raises the question of whether the accused products' method for handling phase steps matches the specific "recentering" technique described in the patent, or if they employ a different, non-infringing stabilization mechanism.

V. Key Claim Terms for Construction

For the ’413 Patent

  • The Term: "status message" (Claim 21)
  • Context and Importance: This term is the central inventive concept. Its construction will determine whether the patent's scope is limited to formal telecommunications protocols or can extend to internal signals within a semiconductor device. Practitioners may focus on this term because the complaint's theory requires applying it to the internal workings of an FPGA, which may not use the formal "SSM" messages discussed in the patent specification.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The claim uses the general phrase "status message indicative of a quality level" without specifying a particular protocol, which could support a construction covering any signal conveying such information. (’413 Patent, col. 16:47-49).
    • Evidence for a Narrower Interpretation: The specification's background and detailed description repeatedly use Synchronization Status Messages (SSMs) from the SONET/SDH standards as the primary example, suggesting the invention was conceived in that specific context. (’413 Patent, col. 2:35-55).

For the ’827 Patent

  • The Term: "recentering the phase comparator" (Claim 28)
  • Context and Importance: This term defines the specific corrective action claimed by the invention. The infringement question will turn on whether the accused PLLs perform this exact operation. Practitioners may focus on this term because different PLL designs might achieve stability after a phase step using methods that do not involve "recentering" the comparator as described in the patent.
  • Intrinsic Evidence for Interpretation:
    • Evidence for a Broader Interpretation: The term itself is not inherently limiting and could be argued to cover any technique that adjusts the operational zero-point or reference of the phase comparator to mitigate a step change.
    • Evidence for a Narrower Interpretation: The specification describes a specific implementation of recentering that involves monitoring and adjusting divide-by-N counters in the feedback loop. (’827 Patent, col. 8:45-67). This embodiment could be used to argue for a narrower construction limited to counter manipulation.

VI. Other Allegations

Indirect Infringement

  • The complaint alleges induced infringement for all asserted patents. The basis for inducement is Defendant’s alleged provision of products along with "documentation and training materials," including specific user guides, that allegedly "cause customers and end users" to operate the products in a directly infringing manner. (Compl. ¶¶100, 126, 152, 171, 194, fn. 30-34).

Willful Infringement

  • The complaint alleges willful infringement for all patents. For the ’413 and ’827 patents, knowledge is alleged from at least the date of service of the complaint. (Compl. ¶¶99, 125). For the ’758, ’983, and ’328 patents, the complaint alleges pre-suit knowledge based on citations to the patents-in-suit in Intel’s own issued patents and published patent applications. (Compl. ¶¶151, 170, 193).

VII. Analyst’s Conclusion: Key Questions for the Case

  • A core issue will be one of evidentiary proof: The complaint's allegations are framed on "information and belief." A key question will be what technical evidence Plaintiff can produce through discovery and expert analysis to show that the internal, proprietary operations of Intel's accused semiconductor products practice the specific methods claimed, as opposed to merely achieving a similar functional result through different means.
  • The case will also likely turn on a question of definitional scope: can terms like "status message" and "recentering the phase comparator," which are described in the patents within specific telecommunication contexts, be construed broadly enough to read on the alleged functionalities within general-purpose FPGAs and Ethernet controllers that may operate under different principles?
  • A central question for willfulness and potential damages enhancement will be one of pre-suit knowledge: for the patents where pre-suit knowledge is alleged, can the fact that Intel's own patent filings cite the patents-in-suit be sufficient to prove that Intel possessed actual knowledge of the patents and their alleged infringement, or will these be characterized as routine citations made during patent prosecution without broader corporate awareness?