DCT
2:18-cv-00064
DIFF Scale Operation Research LLC v. Microsemi Corp
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: DIFF Scale Operation Research, LLC (Delaware)
- Defendant: Microsemi Corporation (Delaware)
- Plaintiff’s Counsel: Capshaw DeRieux, LLP; Berger & Hipskind LLP
- Case Identification: 2:18-cv-00064, E.D. Tex., 03/08/2018
- Venue Allegations: Plaintiff alleges venue is proper in the Eastern District of Texas because Defendant is registered to do business in Texas, maintains offices and facilities in Plano, Texas, and has committed the alleged acts of infringement within the district.
- Core Dispute: Plaintiff alleges that Defendant’s semiconductor timing circuits and network processors infringe a portfolio of six patents related to phase-locked loops, adaptive clock recovery, and protection switching for virtual connections in telecommunications networks.
- Technical Context: The patents address technologies for maintaining stable and accurate timing signals across packet-based networks, a critical function for high-speed data transmission systems where synchronization is essential for data integrity.
- Key Procedural History: The complaint states the patents-in-suit originated with ADC Telecommunications, were later acquired by CommScope, and subsequently assigned to Plaintiff. The complaint notes that Defendant Microsemi has cited patents from the asserted patent families in its own patent applications, suggesting the possibility of pre-suit awareness of the technology.
Case Timeline
| Date | Event |
|---|---|
| 1998-02-20 | Priority Date for ’810 Patent and ’430 Patent |
| 1999-10-01 | Filing Date for ’430 Patent |
| 1999-11-19 | Filing Date for ’328 Patent |
| 2000-10-25 | Filing Date for ’810 Patent |
| 2001-03-02 | Priority Date for ’413 Patent and ’827 Patent |
| 2001-08-03 | Filing Date for ’758 Patent |
| 2002-03-01 | Filing Date for ’413 Patent and ’827 Patent |
| 2003-12-16 | Issue Date for U.S. Patent No. 6,664,827 |
| 2004-04-13 | Issue Date for U.S. Patent No. 6,721,328 |
| 2005-02-22 | Issue Date for U.S. Patent No. 6,859,430 |
| 2005-09-06 | Issue Date for U.S. Patent No. 6,940,810 |
| 2006-09-12 | Issue Date for U.S. Patent No. 7,106,758 |
| 2011-02-01 | Issue Date for U.S. Patent No. 7,881,413 |
| 2018-03-08 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 7,881,413 - “Digital PLL With Conditional Holdover” (Issued Feb. 1, 2011)
The Invention Explained
- Problem Addressed: In communication systems, timing circuits known as phase-locked loops (PLLs) synchronize to a reference clock. If this reference clock is lost or its signal quality degrades, the PLL must enter a "holdover" mode to maintain a stable timing signal and prevent data loss. The patent addresses the problem of a PLL attempting to track a degraded but not completely failed reference signal, which can introduce timing errors into the network (’413 Patent, col. 2:5-24).
- The Patented Solution: The invention proposes a PLL that monitors not just the presence of a reference clock signal but also its quality, typically via a "Synchronization Status Message" (SSM) common in standards like SONET/SDH. If the SSM indicates the quality has dropped below a predetermined target level, the PLL is instructed to enter a holdover state, generating its timing signal based on a previously stored stable frequency, thereby ignoring the poor-quality reference signal (’413 Patent, Abstract; col. 2:35-41).
- Technical Importance: This approach improves network timing reliability by enabling a system to proactively disregard a low-quality timing source, rather than reactively responding only to a complete signal failure (’413 Patent, col. 2:32-41).
Key Claims at a Glance
- The complaint asserts at least independent claim 21 (Compl. ¶91).
- Essential elements of Claim 21 (a system claim) include:
- A phase comparator, a loop filter, and an oscillator arranged in a PLL configuration.
- A processor coupled to the oscillator that receives a status message indicative of a quality level of the reference clock signal.
- A machine-readable medium with instructions for the processor to monitor the status message and place the PLL in a holdover condition if the indicated quality level is below a target level.
- The complaint does not explicitly reserve the right to assert dependent claims.
U.S. Patent No. 6,664,827 - “Direct Digital Synthesizer Phase Locked Loop” (Issued Dec. 16, 2003)
The Invention Explained
- Problem Addressed: When a communication system switches between redundant reference clocks, the abrupt change in the phase of the input signal (a "step change") can cause a conventional PLL to temporarily lose its lock, disrupting the frequency output while it re-synchronizes (’827 Patent, col. 2:18-22).
- The Patented Solution: The patent describes a digital PLL that actively monitors for such a step change. Upon detection, instead of attempting to track the disruptive change, the system "recenters" the digital phase comparator. This action is designed to mitigate the effect of the input phase step on the PLL's output, allowing for a smoother transition and maintaining a more stable timing signal (’827 Patent, Abstract; col. 2:56-62).
- Technical Importance: This technology enhances the stability of timing circuits in systems requiring high availability, where seamless switching between primary and backup timing sources is critical for uninterrupted operation (’827 Patent, col. 8:26-34).
Key Claims at a Glance
- The complaint asserts at least independent claim 28 (Compl. ¶117).
- Essential elements of Claim 28 (a machine-readable medium claim) include instructions to perform a method comprising:
- Sampling values of an error signal indicative of a phase relationship between a reference clock and a feedback signal.
- Monitoring the sampled error signal values for a step change in the phase difference.
- Recentering a phase comparator if a step change is detected.
- The complaint does not explicitly reserve the right to assert dependent claims.
Multi-Patent Capsule: U.S. Patent No. 7,106,758, “Circuit and Method for Service Clock Recovery” (Issued Sep. 12, 2006)
- Technology Synopsis: The patent addresses clock synchronization for circuit emulation services over a packet network. It describes using the fill level of a data buffer at a destination node over multiple time periods to control the frequency of a local service clock, thereby recovering and matching the timing of the source node (Compl. ¶¶46-48, 50).
- Asserted Claims: At least claim 40 (Compl. ¶142).
- Accused Features: The complaint accuses Microsemi’s UFE412, WinPath3, and WinPath4 processors, alleging they contain technology for adaptive clock recovery in packet networks (Compl. ¶¶126, 131).
Multi-Patent Capsule: U.S. Patent No. 6,940,810, “Protection Switching of Virtual Connections at the Data Link Layer” (Issued Sep. 6, 2005)
- Technology Synopsis: The patent describes a method for improving network survivability in a ring network using virtual connections. It discloses a system with two routes (working and protection) where network elements use unidirectional busses to communicate error states between switch fabrics, enabling rapid switching to the protection route when an error occurs on the working route (Compl. ¶¶53, 58-60).
- Asserted Claims: At least claim 13 (Compl. ¶163).
- Accused Features: The complaint accuses Microsemi networking switches (VSC744x series), alleging they perform Layer 2/Layer 3 switching in ring networks with functionality for protection switching of virtual connections (Compl. ¶¶152, 154, 158).
Multi-Patent Capsule: U.S. Patent No. 6,721,328, “Adaptive Clock Recovery for Circuit Emulation Service” (Issued Apr. 13, 2004)
- Technology Synopsis: This patent discloses a system for adaptive clock recovery in a packet network. The invention monitors the fill level of a data buffer at a destination node, identifies a "relative maximum fill level" over a period, and uses this maximum level to control the frequency of a locally generated clock that reads data out of the buffer (Compl. ¶¶63, 66).
- Asserted Claims: At least claim 1 (Compl. ¶185).
- Accused Features: The complaint accuses Microsemi’s optical networking products (PAS740x and PAS65xx series), alleging they include technology for clock recovery in a packet network that involves monitoring a buffer (Compl. ¶¶172, 174, 179).
Multi-Patent Capsule: U.S. Patent No. 6,859,430, “Protection Switching of Virtual Connections” (Issued Feb. 22, 2005)
- Technology Synopsis: This patent, related to the ’810 patent, also describes a system for protecting virtual connections in a network. It claims a system where network elements track the status of virtual connections on each of two routes (working and protection), and upon detecting an error on the working route, the element switches to the protection route for that specific connection (Compl. ¶¶72, 203).
- Asserted Claims: At least claim 10 (Compl. ¶205).
- Accused Features: The complaint accuses the same VSC744x series of networking switches as for the ’810 patent, alleging they comprise network elements that perform protection switching in a ring network (Compl. ¶¶195, 200-201).
III. The Accused Instrumentality
Product Identification
The complaint accuses multiple families of Microsemi products. For the ’413 and ’827 patents, the accused products are primarily timing circuits and ICs, such as the DS3106, ZL30xxx series, and MAX24xxx series (Compl. ¶¶77, 100). For the ’758, ’810, ’328, and ’430 patents, the accused products include network processors (UFE412, WinPath series), optical networking SoCs (PAS series), and Ethernet switches (VSC744x series) (Compl. ¶¶126, 152, 172, 195).
Functionality and Market Context
- The accused timing ICs, such as the DS3106, are described as providing timing for telecommunications line cards used in systems like SONET/SDH and Synchronous Ethernet (Compl. p. 25, p. 29). A key alleged function is the ability to monitor reference clocks and transition to a "holdover" state if a reference fails, generating a stable clock based on a stored frequency value (Compl. p. 26). A datasheet excerpt provided in the complaint for the DS3106 describes its ability to "[h]oldover on Loss of All Input References" (Compl. p. 24).
- The accused networking products are alleged to perform functions central to modern data networks, including adaptive clock recovery for data streams and protection switching to ensure network uptime in the event of a link failure (Compl. ¶¶128, 154). The complaint presents a block diagram for the PAS65xx product showing "Clock Sync" and "Clock Data Recovery" functionality (Compl. p. 44).
IV. Analysis of Infringement Allegations
7,881,413 Patent Infringement Allegations
| Claim Element (from Independent Claim 21) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a phase comparator having a first input for receiving a reference clock signal, a second input for receiving a feedback signal... | The accused '413 Products are alleged to contain a phase comparator for generating a timing signal from a reference clock signal in a phase locked loop (Compl. ¶¶79, 80). | ¶80 | col. 10:60-65 |
| a processor coupled to the oscillator, wherein the processor is further coupled to receive a status message indicative of a quality level of the reference clock signal; | The '413 Products are alleged to include functionality for monitoring a status message from a reference clock source that is indicative of the signal's quality level (Compl. ¶88). | ¶88 | col. 2:35-41 |
| and a machine-readable medium... having instructions stored thereon capable of causing the processor to... place the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level. | The complaint alleges the '413 Products contain functionality to enter a holdover state if the quality level is below a target. A datasheet excerpt states the device enters holdover when it "declares its selected reference invalid" (Compl. p. 26). | ¶89 | col. 3:9-12 |
Identified Points of Contention
- Scope Questions: A central question may be whether the accused product's internal determination that a reference is "invalid" (Compl. p. 26) constitutes monitoring a "status message indicative of a quality level" as recited in the claim. The analysis will explore whether this claim term requires a formal, standardized message (like a SONET SSM, as described in the patent's background) or if it can read on an internal signal or state based on monitoring the reference clock's properties.
- Technical Questions: The complaint asserts, based on product datasheets, that the products perform the claimed functions. A point of contention will be the evidentiary basis showing the internal software and hardware mechanisms of the accused products actually operate in the manner required by the claim's "processor" and "machine-readable medium" limitations.
6,664,827 Patent Infringement Allegations
| Claim Element (from Independent Claim 28) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal; | The complaint alleges the '827 Products contain functionality for sampling an error signal indicative of a phase relationship between a reference clock and a feedback signal (Compl. ¶113). A product datasheet notes that "[p]hase detectors are used to compare a PLL's feedback clock with its input clock" (Compl. p. 30). | ¶¶112, 113 | col. 9:48-55 |
| monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal; and | The '827 Products are alleged to comprise a system for monitoring sampled error signal values for a step change in the phase difference (Compl. ¶115). | ¶115 | col. 2:58-62 |
| recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected. | The complaint alleges the '827 Products include functionality for recentering a phase comparator if a step change is detected (Compl. ¶116). | ¶116 | col. 12:40-44 |
Identified Points of Contention
- Scope Questions: The dispute will likely focus on the meaning of "recentering a phase comparator." The analysis will question what specific technical actions this term covers and whether the accused products' method for handling phase steps, whatever it may be, falls within that scope.
- Technical Questions: The complaint alleges the functionality for "recentering" exists (Compl. ¶116) but does not provide details from datasheets or other sources on the specific mechanism used by the accused products. A key technical question will be what evidence demonstrates that the accused products' response to a step change is the specific "recentering" action claimed, as opposed to a different, potentially non-infringing method of phase correction or re-synchronization.
V. Key Claim Terms for Construction
For the ’413 Patent
- The Term: "status message indicative of a quality level"
- Context and Importance: This term is critical because infringement of claim 21 depends on the accused products receiving and acting upon such a message. The dispute may turn on whether an internal logic state (e.g., declaring a reference "invalid") can be considered a "status message," or if the term requires a discrete, transmitted message packet as exemplified by the SONET/SDH SSMs discussed in the patent.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent claims use the general term "status message" without explicitly limiting it to a specific standard. The specification refers to SSMs as an example of a source for quality information, which could suggest that other sources conveying similar information are also contemplated (’413 Patent, col. 2:35-41).
- Evidence for a Narrower Interpretation: The patent's detailed description is heavily situated in the context of standardized telecommunications networks (SONET/SDH) where SSM has a very specific meaning and format. The abstract links the "conditional holdover" directly to this context, which may support an interpretation limiting the term to such formal messages (’413 Patent, Abstract).
For the ’827 Patent
- The Term: "recentering a phase comparator"
- Context and Importance: This term describes the core inventive concept for handling an input phase step. The infringement analysis will depend on whether the accused products' internal operations perform an action that meets the technical definition of "recentering."
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The summary of the invention describes the purpose of recentering as being to "suppress[] tracking in the event of a step change" and mitigate its effect without moving the phase of the output timing signal (’827 Patent, col. 2:37-41; col. 12:64-67). This functional language may support a construction that covers any digital adjustment achieving this outcome.
- Evidence for a Narrower Interpretation: A specific embodiment describes achieving this recentering by monitoring and adjusting the counts of divide-by-N counters in the PLL's feedback and reference paths (’827 Patent, col. 12:40-52). This detailed description of a specific mechanism could be used to argue for a narrower construction limited to that implementation or its equivalents.
VI. Other Allegations
Indirect Infringement
The complaint alleges induced infringement for all six patents-in-suit. It asserts that Defendant provides documentation, user manuals, datasheets, and training materials that instruct and encourage end-users to operate the accused products in a manner that directly infringes the patent claims (e.g., Compl. ¶¶94, 120, 146, 166, 189, 204).
Willful Infringement
The complaint alleges willful infringement, asserting that the patents are "well-known within the industry" (e.g., Compl. ¶¶95, 121). As a basis for pre-suit knowledge, the complaint notes that Defendant Microsemi has cited patents from the asserted patent families as relevant prior art in its own patent applications (e.g., Compl. ¶¶18, 51, 70, 145, 188). Knowledge is also alleged from the date of service of the complaint.
VII. Analyst’s Conclusion: Key Questions for the Case
This case presents a multifaceted dispute over foundational technologies in network timing and reliability. The outcome will likely depend on the court's resolution of several central questions:
- A core issue will be one of definitional scope: Can the term “status message indicative of a quality level” in the ’413 patent, which is exemplified by formal telecom-standard messages, be construed to cover an internal logic state within a semiconductor chip that declares a reference clock "invalid"?
- A second key question will be one of technical mechanism: Do the accused products’ methods for handling phase discontinuities perform the specific act of “recentering a phase comparator” as claimed in the ’827 patent, or do they employ a fundamentally different, non-infringing technique for phase correction?
- Finally, an overarching evidentiary question will be what facts emerge from discovery. The complaint relies on high-level product datasheets and allegations "on information and belief"; the case will turn on whether the evidence of the accused products' actual internal hardware and software operations substantiates the infringement theories for the six asserted patents.