DIFF Scale Operation Research LLC v. On Semiconductor Corp

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: DIFF Scale Operation Research, LLC (Delaware)
  • Defendant: ON Semiconductor Corporation and Semiconductor Components Industries, LLC (Delaware)
  • Plaintiff’s Counsel: Capshaw DeRieux, LLP; Berger & Hipskind LLP
• Case Identification: 2:18-cv-00077, E.D. Tex., 03/13/2018
• Venue Allegations: Plaintiff alleges venue is proper because Defendant Semiconductor Components Industries, LLC is registered to do business in Texas, both defendants maintain offices and facilities in the Eastern District of Texas, transact business in the district, and have committed acts of infringement in the district. The complaint also notes that many inventors of the asserted patent portfolio are located in or near the district.
• Core Dispute: Plaintiff alleges that Defendant’s semiconductor products for timing and network clock recovery infringe four patents originally developed by ADC Telecommunications, Inc.
• Technical Context: The patents relate to technologies for maintaining stable and accurate timing signals in telecommunications networks, a critical function for synchronizing data transmission and preventing data loss.
• Key Procedural History: The complaint alleges the asserted patent portfolio, originating from ADC Telecommunications, has a significant history, including a $75 million sale of a portion of the portfolio to HTC, which subsequently asserted two of those patents against Apple. The portfolio was later acquired by CommScope in 2015, which then assigned a subset of the patents to the Plaintiff, DIFF Scale Operation Research.

Case Timeline

Date	Event
1999-11-19	U.S. Patent No. 6,721,328 Priority Date
2001-03-02	U.S. Patent No. 7,881,413 Priority Date
2001-03-02	U.S. Patent No. 6,664,827 Priority Date
2001-08-03	U.S. Patent No. 7,106,758 Priority Date
2003-12-16	U.S. Patent No. 6,664,827 Issue Date
2004-04-13	U.S. Patent No. 6,721,328 Issue Date
2006-09-12	U.S. Patent No. 7,106,758 Issue Date
2011-02-01	U.S. Patent No. 7,881,413 Issue Date
2011-05-01	Earliest Accused Product Datasheet Publication (NB3N3010B)
2018-03-13	Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 7,881,413 - Digital PLL with Conditional Holdover

Issued Feb. 1, 2011

The Invention Explained

• Problem Addressed: In high-speed communication networks, timing signals must be precisely maintained. If a primary reference clock signal is lost or degraded, a Phase Locked Loop (PLL) circuit must switch to a "holdover" state to avoid data loss. However, different timing sources have different quality levels (e.g., "strata"), and simply switching based on signal availability alone can lead to using a lower-quality source, introducing network timing errors (’413 Patent, col. 2:5-11, 47-54).
• The Patented Solution: The invention proposes a "conditional holdover" system for a PLL. It uses a processor to monitor not just the presence of a reference clock signal, but also its "quality level," often conveyed via a Synchronization Status Message (SSM). The PLL is instructed to enter or remain in a holdover state if the incoming reference clock's quality is below a predetermined target, even if the signal is otherwise available, thus preventing the system from locking to a low-quality source (’413 Patent, Abstract; col. 10:11-20).
• Technical Importance: This approach allows network equipment to make more intelligent decisions about timing sources, prioritizing stability and quality over mere availability, which is critical for maintaining the integrity of large-scale synchronous networks like SONET/SDH (’413 Patent, col. 2:32-46).

Key Claims at a Glance

• The complaint asserts at least independent claim 21 (Compl. ¶79).
• Claim 21 is for a machine-readable medium with instructions to perform a method comprising the following essential elements:
  • Generating a timing signal from a reference clock signal in a phase locked loop;
  • Monitoring a status message received from a source of the reference clock signal indicative of a quality level of the reference clock signal;
  • Placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level;
  • Performing the method in the order presented.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 6,664,827 - Direct Digital Synthesizer Phase Locked Loop

Issued Dec. 16, 2003

The Invention Explained

• Problem Addressed: A typical Phase Locked Loop (PLL) will attempt to track any "step change" in the phase of an incoming reference clock signal. This tracking can cause a disruptive change in the PLL's output frequency until the signals are re-synchronized, which is undesirable in stable communication systems (’827 Patent, col. 1:18-23).
• The Patented Solution: The invention discloses a PLL that uses a processor to monitor the PLL's error signal for a step change. If a step change is detected, instead of letting the PLL track the change, the system "recenters" the phase comparator. This action suppresses the tracking of the step change, mitigating its effect on the output timing signal and allowing the PLL to maintain a stable output frequency (’827 Patent, Abstract; col. 8:28-44).
• Technical Importance: This method provides a way to absorb abrupt phase shifts in a reference clock—for instance, when switching between primary and secondary timing sources—without propagating that disruption through the network, thereby enhancing overall system stability (’827 Patent, col. 8:45-54).

Key Claims at a Glance

• The complaint asserts at least independent claim 28 (Compl. ¶105).
• Claim 28 is for a machine-readable medium with instructions to perform a method comprising the following essential elements:
  • Sampling values of an error signal, where the error signal indicates a phase relationship between a reference clock and a feedback signal;
  • Monitoring the sampled error signal values for a step change in the phase difference between the reference clock and feedback signals; and
  • Recentering a phase comparator if a step change in the phase difference between the reference clock and feedback signals is detected.
• The complaint does not explicitly reserve the right to assert dependent claims.

U.S. Patent No. 7,106,758 - Circuit and Method for Service Clock Recovery

Issued Sep. 12, 2006

Technology Synopsis

The patent describes a method for recovering a service clock at a destination node in a packet network. It addresses the problem of "cell jitter" (random delays in packet arrival) by calculating control values for a local clock generator (a direct digital synthesis circuit) based on data monitored over a plurality of different time periods, allowing for a more stable and accurate clock recovery than short-term measurements would permit (’758 Patent, Abstract; col. 6:46-51).

Asserted Claims

At least independent claim 40 (Compl. ¶130).

Accused Features

The complaint alleges that the accused transceiver products (AX5043, AX5051, AX5042) infringe by implementing adaptive clock recovery. Specifically, they allegedly receive data packets, store them in a buffer (FIFO), and use the relative maximum fill levels of that buffer over time to control the frequency of a local oscillator, as depicted in a block diagram from the AX5051 datasheet and a FIFO pointer diagram from the AX5043 programming manual (Compl. ¶¶120-129, p.33-34).

U.S. Patent No. 6,721,328 - Adaptive Clock Recovery for Circuit Emulation Service

Issued Apr. 13, 2004

Technology Synopsis

This patent discloses a system for adaptive clock recovery that uses a "peak buffer fill level" as the primary indicator to synchronize a local clock with a source clock. By monitoring the maximum fill level of a data buffer over a period of time, rather than instantaneous fill levels which are susceptible to jitter, the system can control the frequency of a local oscillator to match the source clock rate more reliably (’328 Patent, Abstract; col. 2:2-9).

Asserted Claims

At least independent claim 1 (Compl. ¶152).

Accused Features

The complaint alleges that the accused transceiver products (AX5043, AX5051, AX5042) infringe by using a relative maximum buffer fill level to control a locally generated clock. The allegations point to the products' use of a FIFO buffer and internal communication controller, as shown in a diagram from the AX5042 programming manual, to manage data flow and control clock frequency (Compl. ¶¶145-151, p.38-39).

III. The Accused Instrumentality

Product Identification

• The complaint accuses distinct sets of ON Semiconductor products for each patent.
  • '413 Accused Products: Clock generator products, including NB3H5150, NB3H5150-01, NB3N3010B, NB3N3020, NB3N51032, and NB3N51054 (Compl. ¶64).
  • '827 Accused Products: Programmable clock generator products, including NB3H60113G, NB3H63143G, NB3H73113G, NB3V60113G, and others (Compl. ¶88).
  • '758 & '328 Accused Products: UHF transceiver products, including AX5043, AX5051, and AX5042 (Compl. ¶¶114, 139).

Functionality and Market Context

• The accused products are semiconductor components that perform timing and clock generation functions essential for modern electronics and communication systems. The complaint alleges these products incorporate infringing phase locked loop (PLL) technology (Compl. ¶63).
• The complaint supports its allegations by referencing diagrams from the products' own datasheets. For the '413 Products, a block diagram for the NB3H5150 shows a PLL block receiving a reference clock signal and outputting a timing signal (Compl. ¶72, p.23). This diagram illustrates the core components of the accused functionality. For the '827 Products, a block diagram for the NB3H73113G explicitly annotates a "Phase Detector" within a PLL block, and a separate timing diagram illustrates how clock cycle swings are measured (Compl. ¶90, p.27; ¶96, p.28). For the '758 and '328 products, diagrams show a "Communication Controller & Serial Interface" receiving data packets and managing a FIFO buffer (Compl. ¶121, p.33; ¶147, p.38).
• The complaint alleges these products are widely available to businesses and individuals throughout the U.S. and are sold within the Eastern District of Texas (Compl. ¶¶71, 73, 91, 92).

IV. Analysis of Infringement Allegations

'413 Patent Infringement Allegations

Claim Element (from Independent Claim 21)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
generating the timing signal from a reference clock signal in a phase locked loop	The accused products are systems for generating a timing signal from a reference clock signal in a phase locked loop.	¶75	col. 10:11-13
monitoring a status message received from a source of the reference clock signal indicative of a quality level of the reference clock signal	The accused products allegedly include functionality for monitoring a status message from a reference clock source that indicates the quality level of that clock signal.	¶76	col. 10:14-17
placing the phase locked loop in a holdover condition if the quality level indicated by the status message is below a target level	The accused products allegedly contain functionality to place the PLL in a holdover condition if the monitored quality level is below a target.	¶77	col. 10:18-20

• Identified Points of Contention:
  • Claim Scope Question: The complaint alleges infringement by systems (the '413 Products), but the asserted claim is for a "machine-readable medium" (a component storing software). This raises the question of whether providing a hardware product can directly infringe a claim directed to software instructions.
  • Technical Question: What specific "status message" do the accused products actually monitor, and does its function correspond to the "Synchronization Status Message (SSM)" described in the patent as indicating a "quality level" (e.g., Stratum level)? The complaint does not specify what technical feature performs this monitoring.
  • Functional Question: Does the accused products' response to a change in the input signal constitute "placing the phase locked loop in a holdover condition" as that term is used in the patent, or does it perform a different type of signal management?

'827 Patent Infringement Allegations

Claim Element (from Independent Claim 28)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
sampling values of an error signal, wherein the error signal is indicative of a phase relationship between a reference clock signal and a feedback signal	The accused products allegedly contain functionality for sampling an error signal that is indicative of a phase relationship between a reference clock and feedback signal. A datasheet diagram shows a "Phase Detector" whose output would be such an error signal.	¶101; p.27	col. 8:1-4
monitoring the sampled error signal values for a step change in the phase difference between the reference clock signal and the feedback signal	The accused products allegedly comprise a system for monitoring the sampled error signal values for a step change in phase difference.	¶103	col. 8:5-9
recentering a phase comparator if a step change in the phase difference between the reference clock signal and the feedback signal is detected	The accused products allegedly include functionality for recentering a phase comparator if such a step change is detected.	¶104	col. 8:10-13

• Identified Points of Contention:
  • Claim Scope Question: As with the '413 patent, the complaint asserts a "machine-readable medium" claim against hardware products, raising a question about the theory of direct infringement.
  • Technical Question: What is the specific mechanism in the accused products that constitutes "recentering a phase comparator"? The patent describes a specific software-driven process involving adjusting counter values to suppress tracking (’827 Patent, col. 8:39-61). The complaint does not detail how the accused products perform this function, only that they possess the functionality.
  • Evidentiary Question: What evidence does the complaint provide that the accused products monitor for a "step change" specifically, as opposed to other types of signal variations? The provided datasheet diagram showing clock swing measurements (Compl. p. 28) may relate to jitter but does not explicitly show detection of a "step change."

V. Key Claim Terms for Construction

For the '413 Patent:

• The Term: "holdover condition"

• Context and Importance: This term is central to the invention. The infringement analysis depends entirely on whether the accused products' behavior, when faced with a low-quality input, can be defined as entering a "holdover condition." Practitioners may focus on this term because its definition will determine whether the accused functionality falls within the claim scope.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification describes holdover generally as when a "PLL goes open-loop, i.e., the PLL loses its reference clock signal, or otherwise enters an impaired operating condition" (’413 Patent, col. 2:7-10). This could support a reading that encompasses any state where the PLL is not locked to the external reference.
  • Evidence for a Narrower Interpretation: The abstract and detailed description repeatedly tie the holdover condition to generating the timing signal "without use of an input reference clock signal" (’413 Patent, Abstract; col. 9:15-17). This could support a narrower construction requiring complete disconnection from the input, not merely ignoring its quality messages.

• The Term: "quality level"

• Context and Importance: The novelty of the claim rests on acting based on "quality level," not just signal presence. The dispute will likely involve whether the signal characteristics monitored by the accused products meet the patent's definition of "quality."

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The specification states that timing sources have "quality levels that are often defined in terms of strata" but also mentions "other industry-recognized quality levels," suggesting the term is not limited to formal strata definitions (’413 Patent, col. 2:15-16, 31-32).
  • Evidence for a Narrower Interpretation: The specification's primary example of quality level is the formal "Synchronization Status Message (SSM) of SONET/SDH," which conveys specific, standardized quality information like Stratum levels (’413 Patent, col. 2:35-46). An argument could be made that "quality level" requires this type of formal, messaged-based indicator.

For the '827 Patent:

• The Term: "recenter the digital phase comparator"
• Context and Importance: This is the core inventive step alleged to be infringed. The case may turn on whether the accused products' method of handling a phase shift matches the patent's specific "recentering" mechanism.
• Intrinsic Evidence for Interpretation:
  • Evidence for a Broader Interpretation: The summary states the invention is adapted to "recenter the digital phase comparator if a step change is detected," without limiting the mechanism (’827 Patent, col. 2:61-63). This might support a broader reading covering any corrective action that re-establishes a phase lock without tracking the step change.
  • Evidence for a Narrower Interpretation: The detailed description explains recentering through a specific process of "monitoring and adjusting divide-by-N counters of the frequency dividers" to reset their counts relative to each other (’827 Patent, col. 8:44-61). This could support a narrow construction requiring this specific counter-resetting implementation.

VI. Other Allegations

• Indirect Infringement: The complaint alleges induced infringement for all four patents. The basis is that Defendant provides the accused products along with "documentation and training materials" such as "user manuals, product support, [and] marketing materials" that allegedly instruct and encourage customers to use the products in an infringing manner (Compl. ¶¶ 82, 108, 133, 155).
• Willful Infringement: The complaint alleges willful infringement for all four patents. The allegations are based on claims that the patents are "well-known within the industry" due to numerous citations and that Defendant is infringing in a "willful, wanton, malicious, in bad faith, deliberate, consciously wrongful, flagrant, or characteristic of a pirate" manner (Compl. ¶¶ 83, 109, 134, 156). The complaint also asserts that Defendant had knowledge since at least the service of the complaint (Compl. ¶¶ 81, 107, 132, 154).

VII. Analyst’s Conclusion: Key Questions for the Case

1. A central issue will be one of claim scope and infringement theory: Can Plaintiff prove direct infringement of claims directed to a "machine-readable medium" (Claims 21 of '413 and 28 of '827) by the sale of hardware products (semiconductor chips), or will it need to rely solely on its indirect infringement theories?
2. A key technical question will be one of functional mapping: Do the accused products' operational behaviors, as described in their datasheets, perform the specific functions recited in the claims? For instance, does monitoring a signal for an error equate to monitoring a "status message" for its "quality level" under the '413 patent, and does the accused clock generators' method for handling phase shifts constitute "recentering the phase comparator" as taught by the '827 patent?
3. A critical evidentiary challenge will be one of proof of operation: Beyond the high-level block diagrams in the datasheets, what evidence will show that the accused products actually execute the specific steps of monitoring, comparing, and reacting in the precise manner claimed by the patents-in-suit?