DCT
2:18-cv-00121
Sentient Sensors LLC v. Microsemi Corp
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Sentient Sensors, LLC (New Mexico)
- Defendant: Microsemi Corporation (Delaware); Microsemi SOC Corporation (California); Arrow Electronics, Inc. (New York)
- Plaintiff’s Counsel: The Davis Firm, PC; Kaliko & Associates, LLC
- Case Identification: 2:18-cv-00121, E.D. Tex., 06/20/2018
- Venue Allegations: Plaintiff alleges venue is proper because each Defendant has committed acts of infringement in the Eastern District of Texas and maintains a regular and established place of business within the district, with specific facilities noted in Plano, Texas.
- Core Dispute: Plaintiff alleges that Defendants’ SmartFusion and SmartFusion2 system-on-a-chip products infringe a patent related to multi-chip module smart controllers that combine a microprocessor with an independently operable Field Programmable Gate Array (FPGA).
- Technical Context: The technology concerns integrated, reconfigurable instrument controllers used for monitoring and control in complex systems such as aircraft, industrial machinery, and defense applications.
- Key Procedural History: The complaint alleges that Plaintiff's predecessor-in-interest sent a notice letter to Defendant Microsemi on December 22, 2016, identifying the patent-in-suit and the accused product family, which may be relevant to claims of willful infringement. The complaint also notes that the patented invention was funded in part by the U.S. Air Force under a Cooperative Research and Development Agreement (CRADA).
Case Timeline
| Date | Event |
|---|---|
| 2001-12-19 | '177 Patent Priority Date |
| 2005-08-30 | '177 Patent Issue Date |
| 2016-12-22 | Alleged infringement notice letter sent to Microsemi |
| 2018-06-20 | First Amended Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,938,177 - "Multi-Chip Module Smart Controller"
- Patent Identification: U.S. Patent No. 6,938,177, "Multi-Chip Module Smart Controller", issued August 30, 2005.
The Invention Explained
- Problem Addressed: The patent describes prior art instrument controllers as having significant limitations, particularly an inability to perform truly independent parallel processing because their specialized integrated circuits were controlled by the main microprocessor. These prior systems also lacked flexibility in digitizing analog signals, often using a fixed bit depth for all conversions (e.g., 10-bit). (’177 Patent, col. 2:10-25).
- The Patented Solution: The invention claims a multi-chip module architecture that integrates a microprocessor with a "separately controllable field programmable gate array (FPGA)" that can "run independent of the microprocessor." (’177 Patent, Abstract). This configuration, illustrated in Figure 1, allows the FPGA (170) to function as a reconfigurable, parallel co-processor. The invention also provides for more flexible data acquisition by including analog-to-digital converters capable of operating at different bit depths. (’177 Patent, col. 4:28-34).
- Technical Importance: This architecture provided a platform for creating compact, low-power, and highly flexible controllers capable of "real-time concurrent processing of data" for demanding monitoring and control applications. (Compl. ¶34).
Key Claims at a Glance
- The complaint asserts infringement of at least Claim 1. (Compl. ¶¶44-46).
- Independent Claim 1 of the '177 Patent recites an "instrument controller" with the following essential elements:
- A non-volatile memory component
- A large volatile memory component
- A processor coupled to both memories, itself having an embedded memory for startup without retrieving a program from the non-volatile memory
- At least two internal oscillators for high- and low-frequency operations
- A field programmable gate array (FPGA) coupled to the processor and "configured to run independent processes in parallel with the processor"
- A plurality of analog-to-digital converters capable of digitizing inputs at "at least two possible bit depths"
- Wherein a first portion of the FPGA gates is configured for "signal processing"
- Wherein a second portion of the FPGA gates is configured to operate as a "signal distribution matrix"
- The complaint alleges infringement of "one or more claims," preserving the right to assert additional claims. (Compl. ¶39).
III. The Accused Instrumentality
Product Identification
- The accused instrumentalities are Defendants' "SmartFusion and SmartFusion2 lines of system-on-a-chip (SoC) products." (Compl. ¶44).
Functionality and Market Context
- The complaint describes the accused products as System-on-a-Chip (SoC) devices. (Compl. ¶44). It alleges these SoCs contain a microprocessor, a Field Programmable Gate Array (FPGA), and memory, and that they are used in a wide range of hardware controller solutions. (Compl. ¶33).
- The complaint alleges that these products "meet all limitations of at least Claim 1 of the ’177 Patent" but does not provide specific technical details on their internal architecture or operation. (Compl. ¶¶45-46).
- No probative visual evidence provided in complaint.
IV. Analysis of Infringement Allegations
The complaint alleges that the accused products meet all limitations of Claim 1 but does not provide a detailed, element-by-element infringement analysis. The core allegations are summarized below based on the conclusory statements in the complaint.
'177 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| a non-volatile memory storage component for program and data storage | The complaint alleges the accused SoCs contain a non-volatile memory storage component that meets this limitation. | ¶45, ¶49 | col. 4:24-26 |
| a large volatile memory storage component for additional program and data storage | The complaint alleges the accused SoCs contain a large volatile memory storage component that meets this limitation. | ¶45, ¶49 | col. 4:26-27 |
| a processor...having an embedded memory for storing an initialization program that enables the processor to start up processing without first retrieving a program from the non-volatile memory | The complaint alleges the accused SoCs contain a processor with an embedded memory for startup that meets this limitation. | ¶45, ¶49 | col. 4:57-65 |
| at least two internal oscillators coupled to the processor, for providing clock signals for the low-frequency and high-frequency operations | The complaint alleges the accused SoCs contain at least two internal oscillators that meet this limitation. | ¶45, ¶49 | col. 4:13-19 |
| a plurality of gates arranged in a field programmable gate array...configured to run independent processes in parallel with the processor | The complaint alleges the accused SoCs contain an FPGA configured to run independent processes in parallel with its processor. | ¶45, ¶49 | col. 4:40-44 |
| a plurality of analog-to-digital converters for receiving a plurality of analog inputs, digitizing the analog inputs at one of at least two possible bit depths | The complaint alleges the accused SoCs contain A/D converters that can digitize inputs at variable bit depths. | ¶45, ¶49 | col. 4:28-34 |
| wherein a first portion of the gates in the field programmable gate array is configured to perform signal processing | The complaint alleges the FPGA in the accused SoCs is configured to perform signal processing. | ¶45, ¶49 | col. 4:45-49 |
| wherein a second portion of the gates in the field programmable gate array is configured to operate as a signal distribution matrix for rerouting signals | The complaint alleges the FPGA in the accused SoCs is configured to operate as a signal distribution matrix. | ¶45, ¶49 | col. 9:16-21 |
Identified Points of Contention
- Scope Questions: A primary question will be the interpretation of "configured to run independent processes in parallel with the processor." The dispute may focus on the degree of independence required—whether mere concurrent operation suffices, or if the claim requires that the FPGA be capable of operating without any control or clocking from the main processor.
- Technical Questions: Since the complaint lacks specific evidence, a key technical question is whether the accused SoCs' FPGAs are in fact "configured" to perform the dual functions of "signal processing" and operating as a "signal distribution matrix." Evidence of how these devices are programmed and used by customers will be central to resolving this issue.
V. Key Claim Terms for Construction
The Term: "configured to run independent processes in parallel with the processor"
- Context and Importance: This term appears central to the patent’s asserted novelty over prior art, which the patent characterizes as having processors and co-processors that could not run independently. Practitioners may focus on this term because its construction will likely determine whether the relationship between the processor and FPGA in the accused SoCs falls within the scope of the claim.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The specification states the FPGA "may be operated independently," which could be interpreted as requiring only the capability for independent operation, not a constant state of it. (’177 Patent, col. 4:43-44).
- Evidence for a Narrower Interpretation: The patent repeatedly distinguishes itself from prior art where the co-processor "is controlled and clocked by the microprocessor and cannot run independently." (’177 Patent, col. 2:12-14). This could support an interpretation requiring a high degree of separation in control and/or clocking.
The Term: "signal distribution matrix"
- Context and Importance: This term defines a specific function required of the FPGA. Infringement will depend on whether the routing functionalities of the accused FPGAs meet this definition.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: A plaintiff might argue that this term broadly covers any function where the FPGA is configured to reroute signals between various internal or external connection points.
- Evidence for a Narrower Interpretation: The specification describes using the FPGA "as a cross-bar switching device to select analog or digital signals." (’177 Patent, col. 4:46-47). Figure 2 and its accompanying text illustrate a specific example of this function, which could be used to argue for a narrower construction limited to this type of selective signal routing for monitoring. (’177 Patent, col. 8:15-32).
VI. Other Allegations
Indirect Infringement
- The complaint alleges inducement of infringement against all defendants. It asserts that Defendants had knowledge of the ’177 Patent since at least December 2016 and intended for customers to infringe by providing "use instructions and product literature," as well as "module development kits" that guide users to implement the infringing functionalities. (Compl. ¶¶57, 59, 62).
Willful Infringement
- The complaint alleges that Defendants' infringement has been and continues to be willful. This allegation is primarily based on the assertion that Microsemi gained pre-suit knowledge of the ’177 Patent and its alleged infringement from the December 22, 2016 notice letter. (Compl. ¶¶76-77, 83-84).
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of technical capability and function: can the term "independent processes," which is central to the patent's distinction over prior art, be construed to read on the actual processor-FPGA relationship within the accused SmartFusion SoCs? Resolution will depend on detailed evidence of the accused products' architecture and operational modes.
- A key evidentiary question will be one of configuration and use: does the evidence show that the accused SoCs are actually "configured," either by the defendants or their customers, to use the FPGA to perform the dual functions of "signal processing" and acting as a "signal distribution matrix" as specifically required by the claim, or is there a mismatch between the claimed functions and the products' real-world application?