DCT
2:18-cv-00325
Altair Logix LLC v. Microsoft Corp
Key Events
Complaint
I. Executive Summary and Procedural Information
- Parties & Counsel:
- Plaintiff: Altair Logix LLC (Texas)
- Defendant: Microsoft Corporation (Washington)
- Plaintiff’s Counsel: Direction IP Law
- Case Identification: 2:18-cv-00325, E.D. Tex., 07/30/2018
- Venue Allegations: Plaintiff alleges venue is proper because Defendant maintains a regular and established place of business within the Eastern District of Texas.
- Core Dispute: Plaintiff alleges that Defendant’s Microsoft Surface 2 tablet, which incorporates the NVIDIA Tegra 4 processor, infringes a patent related to dynamically reconfigurable system-on-a-chip architecture.
- Technical Context: The lawsuit concerns the fundamental architecture of systems-on-a-chip (SoCs), which are critical components in mobile devices where balancing high performance for tasks like graphics with power efficiency is paramount.
- Key Procedural History: The complaint notes that asserted Claim 1 was an originally filed claim that issued without amendment and without being rejected as anticipated by prior art, a fact Plaintiff may use to argue for a strong presumption of validity.
Case Timeline
| Date | Event |
|---|---|
| 1997-02-28 | U.S. Patent No. 6,289,434 Priority Date |
| 2001-09-11 | U.S. Patent No. 6,289,434 Issue Date |
| 2018-07-30 | Complaint Filing Date |
II. Technology and Patent(s)-in-Suit Analysis
U.S. Patent No. 6,289,434 - Apparatus and Method of Implementing Systems on Silicon Using Dynamic-Adaptive Run-Time Reconfigurable Circuits for Processing Multiple, Independent Data and Control Streams of Varying Rates
- Patent Issued: September 11, 2001
The Invention Explained
- Problem Addressed: The patent describes a core challenge in chip design: traditional hard-wired, fixed-function circuits offer high performance but are inflexible, while more flexible solutions like general-purpose microprocessors or FPGAs suffer from lower performance or higher cost for complex, real-time tasks (’434 Patent, col. 1:40-49, col. 2:1-33). Fixed-function systems also suffer from "temporal redundancy," where silicon resources are committed to all possible functions even when only a subset is needed at any given time (’434 Patent, col. 2:50-60).
- The Patented Solution: The invention proposes an apparatus of dynamically reconfigurable circuits that can be adapted "in run-time" to meet varying processing demands (’434 Patent, col.3:6-11). This is achieved by using an array of "media processing units" (MPUs), which are aggregates of computational and storage elements that can be re-used in different configurations to eliminate redundancy and reduce cost, thereby achieving the performance of fixed-function hardware with greater flexibility (’434 Patent, col. 2:64 - col. 3:4). The architecture is depicted in the patent's Figure 3, which illustrates multiple media processing units interconnected on a single chip (Compl. ¶23).
- Technical Importance: This architectural approach sought to provide a "system on a chip" that could efficiently handle diverse and demanding tasks like 3D graphics, video processing, and communications by reconfiguring hardware on the fly, a key goal for advancing mobile and embedded computing (Compl. ¶12).
Key Claims at a Glance
- The complaint asserts at least independent Claim 1 (Compl. ¶26).
- The essential elements of independent Claim 1 are:
- An addressable memory for storing data and instructions with a plurality of inputs/outputs.
- A plurality of media processing units, each coupled to the memory's input/outputs.
- Each media processing unit comprises a multiplier, an arithmetic unit, an arithmetic logic unit, and a bit manipulation unit, each with specified data/instruction inputs and outputs.
- The arithmetic logic unit is capable of operating concurrently with the multiplier and the arithmetic unit.
- The bit manipulation unit is capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and the arithmetic unit.
- Each of the plurality of media processing units is capable of performing an operation simultaneously with other media processing units.
- An operation consists of receiving an instruction and data from memory, processing the data, and providing a result back to the memory input/output.
III. The Accused Instrumentality
Product Identification
The "Accused Instrumentality" is identified as the Microsoft Surface 2 tablet (Compl. ¶26). The infringement allegations focus specifically on the NVIDIA Tegra 4 processor contained within the device (Compl. ¶27).
Functionality and Market Context
- The complaint alleges the NVIDIA Tegra 4 processor is a system-on-a-chip that includes multiple "media processing units" in the form of ARM Cortex-A15 multicore processors (Compl. ¶27, ¶28). Each of these cores is alleged to contain a NEON media coprocessor that performs the functions of the claimed multiplier, arithmetic unit, arithmetic logic unit, and bit manipulation unit (Compl. ¶29-32).
- The complaint provides extensive technical documentation and block diagrams to describe the functionality of the Tegra 4's CPU complex, its caches, and the NEON processing engine. The complaint includes a block diagram from NVIDIA's technical documentation highlighting the multiple ARM cores, which it labels "Media processors" (Compl. p. 13).
IV. Analysis of Infringement Allegations
’434 Patent Infringement Allegations
| Claim Element (from Independent Claim 1) | Alleged Infringing Functionality | Complaint Citation | Patent Citation |
|---|---|---|---|
| an addressable memory for storing the data, and a plurality of instructions, and having a plurality of input/outputs... | The memory system of the Accused Instrumentality, which is coupled to the multicore ARM processors and provides instructions and data. The complaint includes a block diagram with a highlighted "Addressable Memory" section. (Compl. p. 11). | ¶27 | col. 55:21-26 |
| a plurality of media processing units, each media processing unit having an input/output coupled to at least one of the addressable memory input/outputs | The multiple ARM Cortex-A15 multicore processors within the NVIDIA Tegra 4 chip. Each is described as a media processing unit coupled to the memory system. | ¶28 | col. 55:27-30 |
| a multiplier having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output... | The NEON media coprocessor within each ARM Cortex-A15 core, which allegedly contains a multiplier (e.g., an "Integer MUL or FP MUL"). | ¶29 | col. 55:31-35 |
| an arithmetic unit having a data input coupled to the media processing unit input/output, an instruction input coupled to the media processing unit input/output, and a data output... | The NEON media coprocessor, which allegedly contains an arithmetic unit (e.g., an "FP ADD"). A diagram of the NEON pipeline showing this unit is provided. (Compl. p. 17). | ¶30 | col. 55:36-40 |
| an arithmetic logic unit...capable of operating concurrently with at least one selected from the multiplier and arithmetic unit; | The NEON media coprocessor, which allegedly contains an arithmetic logical unit (e.g., an "Integer ALU") capable of concurrent operation with the multiplier and arithmetic unit. | ¶31 | col. 55:41-48 |
| a bit manipulation unit...capable of operating concurrently with the arithmetic logic unit and at least one selected from the multiplier and arithmetic unit; | An integer shift unit within the NEON media coprocessor, which is alleged to be a bit manipulation unit capable of the claimed concurrent operation. | ¶32 | col. 55:49-57 |
| each of the plurality of media processors for performing at least one operation, simultaneously with the performance of other operations by other media processing units... | The ARM Cortex-A15 multicore processors are alleged to be capable of performing operations simultaneously with other ARM Cortex-A15 multicore processors on the same chip. | ¶33 | col. 56:21-24 |
| each operation comprising: receiving at the media processor input/output an instruction from the memory; receiving...data from the memory; processing the data...; and providing...the at least one result... | Each ARM Cortex-A15 processor allegedly receives instructions and data from memory via its NEON media coprocessor, processes the data, and provides a result back to the media processor input/output. | ¶34, ¶35 | col. 56:25-33 |
Identified Points of Contention
- Scope Questions: A central question will be whether a general-purpose processor core like the ARM Cortex-A15 falls within the scope of the claimed term "media processing unit". The patent repeatedly describes the invention as a "dynamic-adaptive run-time reconfigurable" apparatus (’434 Patent, Title; col. 3:8-11), which may suggest a much more specific structure than a standard CPU core.
- Technical Questions: The complaint alleges specific concurrent operations between the various units (ALU, BMU, multiplier, etc.). The infringement analysis will depend on whether the accused NVIDIA Tegra 4's NEON engine can, in fact, operate in the precise concurrent modes required by the claim language. The high-level block diagrams in the complaint show the existence of these units but may not be sufficient to prove the specific operational capabilities claimed.
V. Key Claim Terms for Construction
"media processing unit"
- Context and Importance: This term's construction is dispositive. The plaintiff's case hinges on construing this term broadly enough to read on the accused ARM Cortex-A15 processor cores. Conversely, the defense will likely depend on a narrower construction tied to the patent's emphasis on dynamic reconfigurability.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The patent's abstract states the processors "perform arithmetic-type functions, logic functions and bit manipulation functions," and the specification describes the invention as useful for a "myriad of digital processing functions" (’434 Patent, col. 1:33-38). Plaintiff may argue this supports a functional definition that could encompass any processor with these capabilities.
- Evidence for a Narrower Interpretation: The patent is titled Dynamic-Adaptive Run-Time Reconfigurable Circuits. The specification states the "aggregate of the dynamically reconfigurable computational and storage elements" is referred to as a "media processing unit" (’434 Patent, col. 3:14-18) and that cost reduction is achieved by "re-using groups of computational and storage elements in different configurations" (’434 Patent, col. 3:2-4). Defendant may argue this language limits the term to a special-purpose, reconfigurable architecture, not a general-purpose CPU.
"arithmetic unit"
- Context and Importance: Claim 1 independently recites a "multiplier", an "arithmetic unit", and an "arithmetic logic unit". Practitioners may focus on this term to determine if it is a distinct element from the other two, and whether the accused device's architecture truly maps to this tripartite structure.
- Intrinsic Evidence for Interpretation:
- Evidence for a Broader Interpretation: The term could be argued to cover any circuit that performs arithmetic, which might overlap with the function of a multiplier or an ALU in some contexts.
- Evidence for a Narrower Interpretation: The claim's separate recitation of all three terms under the doctrine of claim differentiation suggests each has a distinct meaning. The specification supports this by describing the "Multiplier and adder" section separately from the "Arithmetic Logic Unit" section, implying they are distinct components of the invention (’434 Patent, col. 16:27-61, 16:62-17:9).
VI. Other Allegations
The complaint alleges only a single count of direct infringement and does not contain allegations to support indirect or willful infringement.
VII. Analyst’s Conclusion: Key Questions for the Case
- A core issue will be one of definitional scope: Can the term "media processing unit", rooted in the patent’s description of a "dynamic-adaptive run-time reconfigurable" apparatus, be construed to cover a standard, general-purpose ARM Cortex-A15 processor core? The outcome of this claim construction dispute will likely determine the viability of the infringement case.
- A key evidentiary question will be one of operational mapping: Assuming the term "media processing unit" is construed broadly, does the accused NVIDIA Tegra 4 processor's NEON engine perform the specific, multi-part concurrent operations as strictly required by the limitations of Claim 1, or is there a fundamental mismatch in the technical operation between what is claimed and what the accused device actually does?