Kutt v. Apple Inc

I. Executive Summary and Procedural Information

• Parties & Counsel:
  • Plaintiff: Mers Kutt (Canada)
  • Defendant: Apple Inc. (California), International Business Machines Corporation (New York), et al.
  • Plaintiff’s Counsel: Pro Se
• Case Identification: 2:19-cv-00316, E.D. Tex., 11/25/2019
• Venue Allegations: Venue is based on allegations that Defendants have placed infringing products into the stream of commerce that are used and sold within the Eastern District of Texas.
• Core Dispute: Plaintiff alleges that a wide array of computer, smartphone, and processor products from numerous technology companies infringe a patent related to a method for synchronizing clock signals between a high-speed microprocessor and slower system components.
• Technical Context: The technology addresses performance enhancement in computer systems, particularly methods for upgrading a system with a faster processor while maintaining stable and efficient communication with the original, slower motherboard components.
• Key Procedural History: The complaint states that this case is an "expanded continuation" of a 2004 lawsuit filed by the Plaintiff against Intel Corporation over the same patent. It also notes that a complaint filed in 2012 was dismissed without prejudice for lack of standing, an issue the Plaintiff claims has since been resolved by formally registering the patent assignment.

Case Timeline

Date	Event
1993-03-29	U.S. Patent No. 5,506,981 Priority Date
1996-04-09	U.S. Patent No. 5,506,981 Issue Date
2004-05-24	Prior infringement case filed against Intel
2012-12-20	Prior complaint filed and later dismissed
2019-11-25	Current Amended Complaint Filing Date

II. Technology and Patent(s)-in-Suit Analysis

U.S. Patent No. 5,506,981 - "Apparatus and method for enhancing the performance of personal computers"

Issued April 9, 1996 (’981 Patent).

The Invention Explained

• Problem Addressed: The patent describes the challenge of upgrading a personal computer by replacing its original, slow microprocessor with a newer, faster one ('981 Patent, col. 1:9-15). A key problem is that the new, high-speed processor must still communicate with the computer’s other, slower components. Prior solutions that involved slowing down the new processor for these communications, or using independently-running clocks, created significant performance penalties due to synchronization delays ('981 Patent, col. 1:40-57).
• The Patented Solution: The invention is an "accelerator board" containing the new, faster microprocessor. Its core innovation is a method for generating the processor's high-speed clock signal in a way that remains synchronized with the original system's slower clock. It achieves this by first using a "sub-hARMonic generator" to derive a low-frequency signal that is a common denominator of both the slow system clock and the desired fast processor clock. A phase-locked loop (PLL) oscillator then uses this stable sub-hARMonic signal to generate the final high-frequency clock for the new processor. This ensures a "known phase relationship" between the fast and slow clocks, facilitating efficient data transfer. ('981 Patent, Abstract; Fig. 1).
• Technical Importance: The described method provided a way to achieve significant performance gains on existing computer systems in a cost-effective manner, by enabling a faster-clocked processor to operate stably and efficiently within the constraints of a slower legacy system architecture ('981 Patent, col. 2:32-54).

Key Claims at a Glance

• The complaint asserts independent claim 5. (Compl. p. 48).
• The essential elements of independent claim 5 are:
  • An accelerator board for use in replacing a microprocessor, comprising:
  • an enhanced microprocessor for operation by a second clock signal having a higher frequency than a first clock signal;
  • bus means for transmitting the first clock signal to the accelerator board;
  • a sub-harmonic generator responsive to the first clock signal, which generates a sub-harmonic signal whose frequency is a common denominator of the first and second clock frequencies; and
  • a phase locked loop oscillator that uses the sub-harmonic signal to generate the second clock signal in a known phase relationship with the first clock signal.

III. The Accused Instrumentality

Product Identification

The complaint broadly accuses "PCs and PC-based products," including smartphones, sold by the defendants since 1996 (Compl. ¶74). Specific infringement allegations are directed at Apple products, including the iPhone, iPod, iPad, and Mac products (Compl. ¶200), with the most detailed allegations targeting the Apple iPhone 4 and its A4 chip (Compl. p. 48).

Functionality and Market Context

• The complaint alleges that the accused products, exemplified by the Apple A4 chip, contain circuitry that performs the functions of the patented invention. Specifically, it alleges that the chips generate multiple clock signals (e.g., a "CPUCLK" and an "HCLK") and use a "signal generator" to create a "sub-harmonic signal" that is a common denominator of the other clock frequencies, thereby infringing the '981 Patent (Compl. p. 48).
• The complaint alleges that the patented technology is responsible for the performance that enabled the "whirlwind success" of the iPhone and that at least 7 billion products sold since 1996 incorporate the invention (Compl. ¶74, ¶97). A chart depicting worldwide PC sales from 1996-2017 is provided to illustrate the scale of the accused market. This chart shows PC sales growing from 70.9 million units in 1996 to a peak of 365.4 million in 2011 (Compl. p. 36).

IV. Analysis of Infringement Allegations

Claim Chart Summary

The following table summarizes the infringement allegations for Claim 5 against the Apple iPhone 4, based on the claim chart provided in the complaint.

Claim Element (from Independent Claim 5)	Alleged Infringing Functionality	Complaint Citation	Patent Citation
an enhanced microprocessor for operation by a second clock signal having a second clock frequency higher than said first frequency;	The Apple iPhone 4 includes an Apple A4 chip with an ARM Cortex processor core which operates by a CPUCLK clock signal (second clock signal) at a frequency higher than the HCLK clock signal (first clock signal).	¶48	col. 3:31-34
bus means for transmitting said first clock signal to said accelerator board;	Traces on the substrate of the Apple A4 chip connect to the motherboard, allegedly constituting bus means for transmitting the first clock signal.	¶48	col. 3:38-41
a sub-harmonic generator responsive to said first clock signal for generating a sub-harmonic signal...the frequency of said sub-harmonic signal being a common denominator of said first clock frequency and said second clock frequency;	A signal generator allegedly responds to the HCLK signal to generate an HCLKEXT signal (sub-harmonic signal) with a frequency (e.g., 35Mhz) that is a common denominator of the first clock (e.g., 70Mhz) and second clock (e.g., 210Mhz) frequencies.	¶48	col. 5:26-32
a phase locked loop oscillator responsive to said sub-harmonic signal for generating a second clock signal...in known phase relationship with said first clock signal...	A phase-locked loop oscillator is alleged to be responsive to the HCLKEXT signal to generate the CPUCLK signal in a known phase relationship with the HCLK signal.	¶49	col. 7:10-18

Identified Points of Contention

• Scope Questions: A primary question may be whether the term "accelerator board for use in replacing the microprocessor," as recited in the claim preamble, can be construed to cover a modern, integrated System-on-a-Chip (SoC) like the Apple A4. The patent repeatedly describes a physical plug-in board replacement for a socketed microprocessor ('981 Patent, Fig. 1; col. 2:32-34), raising the question of whether an integrated, single-chip solution falls within the claim's scope.
• Technical Questions: The complaint alleges that the A4 chip generates specific clock frequencies and a "common denominator" sub-harmonic signal (Compl. p. 48). A key technical question for the court will be what evidence supports this assertion. The infringement analysis will depend on whether the accused chip's internal clocking architecture actually performs the specific functions of a "sub-harmonic generator" and "phase locked loop oscillator" in the manner claimed by the patent.

V. Key Claim Terms for Construction

• The Term: "accelerator board"

• Context and Importance: The construction of this term, which appears in the preamble and body of Claim 5, is central to the dispute. If the term is limited to a physically separate printed circuit board that plugs into a socket on a motherboard, it may not read on the accused integrated SoCs, where all components reside on a single piece of silicon.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: A party might argue that the term should be interpreted functionally to mean any apparatus that accelerates a processor, regardless of its physical form. The focus could be placed on the electronic circuit functions rather than the physical packaging.
  • Evidence for a Narrower Interpretation: The specification consistently describes the invention as an "accelerator board plug-in replacement to the microprocessor socket" ('981 Patent, col. 2:32-34) and Figure 1 explicitly depicts a "SOCKET" into which the accelerator board connects. This language may support a narrower construction requiring a physically separate and replaceable module.

• The Term: "sub-harmonic generator"

• Context and Importance: This term describes the core technical mechanism of the invention. Its definition will determine whether the clock management circuits within modern SoCs perform the same function in the same way as what is claimed. Practitioners may focus on this term because the allegation that a modern SoC uses this specific 1990s-era technique will require substantial technical proof.

• Intrinsic Evidence for Interpretation:

  • Evidence for a Broader Interpretation: The term could be argued to broadly cover any circuit that generates a lower-frequency signal that is a common denominator of two other clock signals for synchronization purposes. The abstract refers to "deriving a sub-harmonic frequency," suggesting a functional definition ('981 Patent, Abstract).
  • Evidence for a Narrower Interpretation: The specification describes a specific implementation of the generator using a delay line and logic gates ('981 Patent, Fig. 3a; col. 6:31-62). A party could argue that the term should be limited to this disclosed structure or its equivalents, potentially excluding different types of frequency-dividing circuits used in modern processors.

VI. Other Allegations

• Indirect Infringement: The complaint alleges inducement against multiple parties. For example, it alleges ARM induces infringement by licensing infringing processor designs to other companies (Compl. ¶103, ¶210), and that Apple induces infringement by creating and selling infringing products with knowledge (Compl. ¶194).
• Willful Infringement: Willfulness is alleged against all defendants, based on purported pre-suit knowledge of the patent and the technology (Compl. ¶195, ¶202, ¶205). The complaint points to the long history of the technology and prior litigation as evidence of this knowledge.

VII. Analyst’s Conclusion: Key Questions for the Case

• A core issue will be one of architectural scope: can the claim term "accelerator board," rooted in the patent's disclosure of a physical plug-in card for 1990s PCs, be construed to cover the highly integrated, single-chip System-on-a-Chip (SoC) architectures used in the accused modern smartphones and processors?
• A key evidentiary question will be one of technical proof: what factual evidence underlies the complaint's detailed allegations about the internal clocking mechanisms of the accused products, and does that evidence demonstrate that they operate using the specific "sub-harmonic generator" method required by the claims?
• The case may also turn on the doctrine of equivalents: if the accused products are found not to literally infringe, a central question will be whether their internal clock management systems perform substantially the same function, in substantially the same way, to achieve substantially the same result as the claimed invention.